github-mirrors

docker-radarr

Dockerfile 0 0

hacktoberfest

Updated 2026-08-02 11:48:43 -06:00

el_poblador

Go 0 0

FOSS Catan clone

Updated 2026-08-01 15:56:42 -06:00

picorv32

Verilog 0 0

PicoRV32 - A Size-Optimized RISC-V CPU

Updated 2026-07-30 23:59:00 -06:00

ibex

SystemVerilog 0 0

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

cpucore hardware risc-v rv32

Updated 2026-07-28 07:11:21 -06:00

piwigo

Dockerfile 0 0

hacktoberfest

Updated 2026-07-25 10:13:49 -06:00

operese

Rust 0 0

Windows to Linux migration tool. Alpha-quality and not yet recommended for non-development use.

Updated 2026-07-24 03:07:52 -06:00

cvw

SystemVerilog 0 0

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

Updated 2026-07-19 06:38:43 -06:00

docker-qbittorrent

Dockerfile 0 0

hacktoberfest

Updated 2026-07-19 02:59:43 -06:00

cve2

SystemVerilog 0 0

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

Updated 2026-07-17 12:41:16 -06:00

kiwix-tools

C++ 0 0

Command line Kiwix tools: kiwix-serve, kiwix-manage, ...

daemon http kiwix library offline zim

Updated 2026-07-11 10:19:52 -06:00

serv

Verilog 0 0

SERV - The SErial RISC-V CPU

asic fpga risc-v verilog

Updated 2026-07-10 06:43:13 -06:00

flame