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cve2
SystemVerilog 0 0
The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
Updated 2025-12-05 02:33:13 -07:00
sonarr
C# 0 0
Smart PVR for newsgroup and bittorrent users.
Updated 2025-12-04 21:17:34 -07:00
immich-helm-charts
Starlark 0 0
Helm chart implementation of Immich
Updated 2025-12-04 06:00:16 -07:00
wekan
JavaScript 0 0
The Open Source kanban (built with Meteor). Keep variable/table/field names camelCase. For translations, only add Pull Request changes to wekan/i18n/en.i18n.json , other translations are done at https://app.transifex.com/wekan/ only.
javascript docker-image foss kanban meteor real-time sandstorm snapcraft wekan
Updated 2025-12-04 02:58:44 -07:00
docker-qbittorrent
Dockerfile 0 0
hacktoberfest
Updated 2025-12-04 02:54:48 -07:00
kiwix-build
Python 0 0
Kiwix & openZIM build engine
Updated 2025-12-03 16:00:20 -07:00
vortex
C++ 0 0
Updated 2025-12-03 14:54:00 -07:00
it-tools
Vue 0 0
Collection of handy online tools for developers, with great UX.
converter developer-productivity developer-tools frontend javascript productivity tool tools typescript vuejs website
Updated 2025-12-03 12:56:12 -07:00
ibex
SystemVerilog 0 0
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
cpucore hardware risc-v rv32
Updated 2025-12-03 10:21:15 -07:00
invidious-companion
TypeScript 0 0
Invidious companion for handling video streams - based on youtube.js
Updated 2025-12-03 04:48:10 -07:00
docker-bazarr
Dockerfile 0 0
hacktoberfest
Updated 2025-12-02 14:30:50 -07:00
pleroma
Elixir 0 0
Pleroma backend
Updated 2025-12-02 11:36:51 -07:00
audiobookshelf
JavaScript 0 0
Self-hosted audiobook and podcast server
audiobook-manager audiobooks audiobookshelf podcasts self-hosted
Updated 2025-12-01 16:13:15 -07:00
kiwix-tools
C++ 0 0
Command line Kiwix tools: kiwix-serve, kiwix-manage, ...
daemon http kiwix library offline zim
Updated 2025-12-01 02:51:36 -07:00
VexRiscv
Assembly 0 0
A FPGA friendly 32 bit RISC-V CPU implementation
cpu fpga riscv soc softcore spinalhdl verilog vhdl
Updated 2025-11-30 23:59:45 -07:00