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github-mirrors/ neorv32

VHDL 0 0

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

asip axi cpu embedded fpga microcontroller neorv32 on-chip-debbuger processor risc-v riscv rtl rtos rv32 safety soc soft-core system-on-chip verilog vhdl

Updated 2025-06-22 15:11:25 -04:00

github-mirrors/ VexRiscv

Assembly 0 0

A FPGA friendly 32 bit RISC-V CPU implementation

cpu fpga riscv soc softcore spinalhdl verilog vhdl

Updated 2025-06-08 13:29:41 -04:00

github-mirrors/ serv

Verilog 0 0

SERV - The SErial RISC-V CPU

asic fpga risc-v verilog

Updated 2025-06-05 02:56:43 -04:00