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Pebble

C 0 0

This is the latest version of the internal repository from Pebble Technology providing the software to run on Pebble watches. Proprietary source code has been removed from this repository and it will not compile as-is. This is for information only.

Updated 2025-02-25 12:02:51 -07:00

yuzu

C++ 0 0

Nintendo Switch emulator

emulation emulator switch c-plus-plus cpp

Updated 2025-02-06 07:52:53 -07:00

ryujinx

C# 1 0

Experimental Nintendo Switch Emulator written in C#

csharp dotnet dotnet-core emulation emulator switch

Updated 2025-02-06 07:52:03 -07:00

picorv32

Verilog 0 0

PicoRV32 - A Size-Optimized RISC-V CPU

Updated 2024-06-17 00:20:13 -06:00

homebox

Go 0 0

Homebox is the inventory and organization system built for the Home User

hacktoberfest hacktoberfest2022

Updated 2024-06-11 07:57:57 -06:00

docker-openvpn-client

Shell 0 0

OpenVPN client with killswitch and proxy servers; built on Alpine

openvpn-client proxy-server socks-proxy vpn-tunnel

Updated 2024-03-16 12:17:27 -06:00

flame

TypeScript 0 0

Flame is self-hosted startpage for your server. Easily manage your apps and bookmarks with built-in editors.

self-hosted homepage startpage

Updated 2023-07-23 06:51:23 -06:00

picframe-colepd

C 0 0

A WiFi picture frame allowing for remote photo uploads, using an ESP32-C3 and a 5.6" color E-ink display

Updated 2023-04-23 00:29:58 -06:00

AAXtoMP3

Shell 0 0

Convert Audible's .aax filetype to MP3, FLAC, M4A, or OPUS

audiobooks aax audible drm drm-restrictions ffmpeg mp3

Updated 2023-01-29 10:29:36 -07:00

MMM-piwigo-photo-wheel

JavaScript 0 0

Updated 2022-11-20 01:11:37 -07:00

ReonV

VHDL 0 0

ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 architecture, now changed to RISC-V ISA.

Updated 2022-09-30 19:16:01 -06:00

VexRiscvBPluginGenerator

C 0 0

Updated 2022-08-27 00:33:22 -06:00

harv

VHDL 0 0

HARV - HArdened Risc-V

fault-tolerance fpga processor reliability risc-v rv32i

Updated 2022-03-10 11:29:46 -07:00

RPU

VHDL 0 0

Basic RISC-V CPU implementation in VHDL.

apache2-license cpu fpga risc-v riscv vhdl

Updated 2020-09-11 17:23:50 -06:00

maestro

VHDL 0 0

A 5 stage-pipeline RV32I implementation in VHDL

Updated 2020-03-12 18:45:17 -06:00