github-mirrors

picorv32

Verilog 0 0

PicoRV32 - A Size-Optimized RISC-V CPU

Updated 2024-06-17 02:20:13 -04:00

homebox

Go 0 0

Homebox is the inventory and organization system built for the Home User

hacktoberfest hacktoberfest2022

Updated 2024-06-11 09:57:57 -04:00

docker-openvpn-client

Shell 0 0

OpenVPN client with killswitch and proxy servers; built on Alpine

openvpn-client proxy-server socks-proxy vpn-tunnel

Updated 2024-03-16 14:17:27 -04:00

flame

TypeScript 0 0

Flame is self-hosted startpage for your server. Easily manage your apps and bookmarks with built-in editors.

self-hosted homepage startpage

Updated 2023-07-23 08:51:23 -04:00

picframe-colepd

C 0 0

A WiFi picture frame allowing for remote photo uploads, using an ESP32-C3 and a 5.6" color E-ink display

Updated 2023-04-23 02:29:58 -04:00

AAXtoMP3

Shell 0 0

Convert Audible's .aax filetype to MP3, FLAC, M4A, or OPUS

audiobooks aax audible drm drm-restrictions ffmpeg mp3

Updated 2023-01-29 12:29:36 -05:00

MMM-piwigo-photo-wheel

JavaScript 0 0

Updated 2022-11-20 03:11:37 -05:00

ReonV

VHDL 0 0

ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 architecture, now changed to RISC-V ISA.

Updated 2022-09-30 21:16:01 -04:00

VexRiscvBPluginGenerator

C 0 0

Updated 2022-08-27 02:33:22 -04:00

harv

VHDL 0 0

HARV - HArdened Risc-V

fault-tolerance fpga processor reliability risc-v rv32i

Updated 2022-03-10 13:29:46 -05:00

RPU

VHDL 0 0

Basic RISC-V CPU implementation in VHDL.

apache2-license cpu fpga risc-v riscv vhdl

Updated 2020-09-11 19:23:50 -04:00

maestro

VHDL 0 0

A 5 stage-pipeline RV32I implementation in VHDL

Updated 2020-03-12 20:45:17 -04:00