riscv32

Author	SHA1	Message	Date
Blizzard Finnegan	f2bb3c66c7	Include extra documentation for ISA	2025-02-06 10:08:59 -05:00
Blizzard Finnegan	ec65e86ba0	Merge branch 'main' of ssh://git.blizzard.systems:25/blizzardfinnegan/riscv32	2025-02-06 10:00:10 -05:00
Blizzard Finnegan	3debeda82b	Begin implementation of memory interface and PC Remove FPU file; that is an entire project in and of itself.	2025-02-06 09:47:52 -05:00
Blizzard Finnegan	a7d3f61326	Add additional comments, continue cleaning	2025-01-25 17:43:28 -05:00
Blizzard Finnegan	7acf129077	Merge register files into single file Update constants with more information	2025-01-22 21:25:42 -05:00
Blizzard Finnegan	b4d99ecdb9	Continue basica ALU functions	2025-01-20 11:45:46 -05:00
Blizzard Finnegan	8918668abd	INclude makefile	2024-12-08 19:28:36 -05:00
Blizzard Finnegan	cf5643fa15	Start implementing execution units	2024-12-03 22:16:16 -05:00
Blizzard Finnegan	48d2cf2842	Add note for compressed decode	2024-12-03 13:46:34 -05:00
Blizzard Finnegan	591b08eb25	Start compressed decoder	2024-12-03 13:44:08 -05:00
Blizzard Finnegan	fcd108be5c	Finish basic instruction decoder Generalise destination, reg1, reg2	2024-12-03 12:55:48 -05:00
Blizzard Finnegan	5d2eb1b25d	Continue instruction decoder	2024-12-03 11:49:34 -05:00
Blizzard Finnegan	cc5e97b0ee	Start developing instruction decoder So many outputs....	2024-12-02 22:07:37 -05:00
Blizzard Finnegan	918c0e3a1e	Add reference docs	2024-11-04 22:04:45 -05:00
Blizzard Finnegan	91242e78dd	Move old info into new repo	2024-11-04 22:02:35 -05:00
Blizzard Finnegan	2c3bb0f877	Initial commit	2024-11-04 21:56:55 -05:00

16 commits