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github-mirrors/ cva6

SystemVerilog 0 0

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

ariane asic cpu fpga risc-v rv64gc systemverilog-hdl

Updated 2025-04-07 14:50:00 -04:00

github-mirrors/ cvw

SystemVerilog 0 0

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

Updated 2025-04-07 14:23:38 -04:00

github-mirrors/ ibex

SystemVerilog 0 0

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

cpucore hardware risc-v rv32

Updated 2025-04-03 04:48:00 -04:00

github-mirrors/ cve2

SystemVerilog 0 0

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

Updated 2025-03-25 04:27:12 -04:00

github-mirrors/ cva5

SystemVerilog 0 0

The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.

Updated 2025-03-17 23:19:22 -04:00