The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Updated 2025-04-17 21:30:40 -04:00
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
Updated 2025-04-17 16:08:19 -04:00
The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
Updated 2025-04-10 08:06:34 -04:00
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Updated 2025-04-03 04:48:00 -04:00
The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
Updated 2025-03-17 23:19:22 -04:00