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github-mirrors/ serv

Verilog 0 0

SERV - The SErial RISC-V CPU

asic fpga risc-v verilog

Updated 2025-06-05 02:56:43 -04:00

github-mirrors/ picorv32

Verilog 0 0

PicoRV32 - A Size-Optimized RISC-V CPU

Updated 2024-06-17 02:20:13 -04:00