github-mirrors/RPU
1
0
Fork 0
mirror of https://github.com/Domipheus/RPU.git synced 2025-04-18 19:15:13 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions
Basic RISC-V CPU implementation in VHDL.
8 commits 1 branch 1 tag 189 KiB
Find a file
Colin Riley 96b86f1dc2 Basic core execution simulator testbench. No memory subsystem, so will only execute from fixed array of instructions - but easy to use in the sim.
2018-11-16 22:43:47 +00:00
tests Basic core execution simulator testbench. No memory subsystem, so will only execute from fixed array of instructions - but easy to use in the sim. 2018-11-16 22:43:47 +00:00
vhdl CSR Unit implemented with all CSR operational modify operations (write, set, clear). Not all CSRs are supported as yet, but cycles, instret and some of the machine identifiers are. Also two R/W locations at 0x400 and 0x401 for testing. 2018-11-16 22:39:57 +00:00
LICENSE Add License 2018-09-17 23:24:42 +01:00
README.md Rearrange readme and add overview image. 2018-09-11 23:58:33 +01:00
rpu_core_diagram.png Initial commit. Tested on ArtyS7-RPU-SoC and passes SD bootloader and DDR3 memory testing. 2018-09-11 23:53:41 +01:00

README.md

RPU

Basic RISC-V CPU implementation in VHDL.

This is a RV32I ISA CPU implementation, based off of my TPU CPU design. It is very simple, is missing several features, but can run rv32i-compiled GCC toolchain binaries at over 200MHz on a Digilent Arty S7-50 board, built with Xilinx Spartan 7 tools.

Please let me know if you are using any of the RPU design in your own projects! I am contactable on twitter @domipheus.

Implementation

RPU Core overview

Implementation detail is written about via blogs available at http://labs.domipheus.com/blog/designing-a-cpu-in-vhdl-part-15-introducing-rpu/

The tests in the repo are incredibly old and basic, and included only as a baseline to help. They will be expanded upon in time.