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Basic RISC-V CPU implementation in VHDL.

apache2-license cpu fpga risc-v riscv vhdl

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Colin Riley cc388e3a90 Start of CSR and interrupt support for machine-mode level operations. No testbenches and the CSR operations are not fixed up yet. Some basic read values are included but as the register write logic is not edited to take values from the CSR unit rather than ALU any reads will result in the incorrect data being stored into rD.		2018-11-12 00:17:16 +00:00
tests	Initial commit. Tested on ArtyS7-RPU-SoC and passes SD bootloader and DDR3 memory testing.	2018-09-11 23:53:41 +01:00
vhdl	Start of CSR and interrupt support for machine-mode level operations. No testbenches and the CSR operations are not fixed up yet. Some basic read values are included but as the register write logic is not edited to take values from the CSR unit rather than ALU any reads will result in the incorrect data being stored into rD.	2018-11-12 00:17:16 +00:00
LICENSE	Add License	2018-09-17 23:24:42 +01:00
README.md	Rearrange readme and add overview image.	2018-09-11 23:58:33 +01:00
rpu_core_diagram.png	Initial commit. Tested on ArtyS7-RPU-SoC and passes SD bootloader and DDR3 memory testing.	2018-09-11 23:53:41 +01:00

README.md

RPU

Basic RISC-V CPU implementation in VHDL.

This is a RV32I ISA CPU implementation, based off of my TPU CPU design. It is very simple, is missing several features, but can run rv32i-compiled GCC toolchain binaries at over 200MHz on a Digilent Arty S7-50 board, built with Xilinx Spartan 7 tools.

Please let me know if you are using any of the RPU design in your own projects! I am contactable on twitter @domipheus.

Implementation

Implementation detail is written about via blogs available at http://labs.domipheus.com/blog/designing-a-cpu-in-vhdl-part-15-introducing-rpu/

The tests in the repo are incredibly old and basic, and included only as a baseline to help. They will be expanded upon in time.