github-mirrors/VexRiscv
1
0
Fork 0
mirror of https://github.com/SpinalHDL/VexRiscv.git synced 2025-04-22 13:07:10 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions
1582 commits 39 branches 2 tags 14 MiB
Commit graph

1582 commits

This branch
This branch
All branches
Author SHA1 Message Date
Dolu1990
a40d5f19b2 Fix MMU A and D flag handeling 2023-02-23 12:00:08 +01:00
Dolu1990
344b2d4eda TestIndividual supervisor missing CSR=yes 2023-02-23 11:59:13 +01:00
Dolu1990
9605b663bf D$ now support thightly coupled ram. 
Add IBusDBusCachedTightlyCoupledRam plugin
 2023-02-22 15:26:14 +01:00
Dolu1990
220b599c9a Fix d$ invalidation when the mmu is enabled 2023-02-22 13:16:02 +01:00
Dolu1990
366f09a14a fix too early 2023-02-19 09:51:54 +01:00
Dolu1990
15a665af53 fix too early 2023-02-19 09:51:18 +01:00
Dolu1990
c57da3c7dc fix too early 2023-02-19 09:50:41 +01:00
Dolu1990
d078297496 fix too early 2023-02-19 09:48:59 +01:00
Dolu1990
a780eec616 Merge branch 'debug-debug' into dev 2023-02-13 10:04:41 +01:00
Dolu1990
33e820bdf9 FPU now implement a less pessismitic dirty logic 2023-02-08 15:16:53 +01:00
Dolu1990
3ae51cdeb8 Fix fpu csr access on fs===0 now also trap 2023-02-08 14:44:04 +01:00
Dolu1990
692f604dd5 Fix VexRiscvSmpClusterGen without linux debug minimal features 2023-02-08 11:28:21 +01:00
Dolu1990
cbc89093b3 fpu csr access on fs===0 now also trap 2023-02-07 10:18:08 +01:00
Dolu1990
9acc5ddc1c Fix FPU access trap on fs = 0 #297 2023-02-06 11:44:44 +01:00
Dolu1990
fc9a9d25ed sync 2023-02-06 11:43:49 +01:00
Dolu1990
e83bc5312e Fix RVC decompressor don't care #296 2023-01-18 15:19:59 +01:00
Dolu1990
2bc6e70f03 Fix RVC decompressor don't care #296 2023-01-18 15:19:33 +01:00
Dolu1990
7d3a862183 Fix Litex cluster scopt update 2023-01-16 18:10:51 +01:00
Dolu1990
aea2e90d1e Upgrade to SBT 1.6.0 2023-01-16 17:58:23 +01:00
Dolu1990
94f2ea6dec
Merge pull request #289 from buncram/expose-satp 
Expose satp
 2023-01-16 12:45:02 +01:00
Dolu1990
0aa6e0573d
shorter satp export 2023-01-16 12:43:01 +01:00
Dolu1990
ed5babaaab
shorter syntax on privilege export 2023-01-16 12:39:55 +01:00
buncram
2297f8aea0 also need to expose privilege state 
turns out SATP is not enough to figure out what code you're running,
because the kernel code is mapped into all userspace's virtual memory
areas. You also need the privilege state to be exported.

This creates an option to export those bits.
 2023-01-16 02:16:25 +08:00
Dolu1990
0963eb06bd
Merge pull request #294 from chiangkd/master 
Fix invalid hyperlink
 2023-01-13 16:25:30 +01:00
chiangkd
6650d0549d Fix invalid hyperlink 2023-01-12 20:51:58 +08:00
Dolu1990
c8dff13391
Merge pull request #291 from chiangkd/master 
Fix incorrect comment
 2023-01-02 09:56:49 +01:00
chiangkd
df52fab7d1 Fix incorrect comment 2022-12-24 20:41:57 +08:00
Dolu1990
8a6a926401
Merge pull request #288 from betrusted-io/expand-satp 
Expand SATP register to 22 bits per spec
 2022-12-20 16:05:13 +01:00
buncram
11f391eadf Merge remote-tracking branch 'origin/expand-satp' into expose-satp 2022-12-20 19:31:15 +08:00
bunnie
bf3521f86a Expand SATP register to 22 bits per spec 
Vex only implements a 32-bit PA which does not take advantage
of the potetnial 32-bit space in Sv32 mode. Very reasonably,
Vex simply discards the top two unused bits.

However, the spec does require that the register occupy all 22
bits and it is possible for the OS to use the extra bits up top
for some bookkeeping purpose. This commit proposes to expand the
register to occupy the full 22 bits in case an OS is written
to utilize the full width of the register as written in the spec.
 2022-12-20 19:25:47 +08:00
buncram
b86047901a add flag to expose SATP externally 2022-12-19 19:03:33 +08:00
Dolu1990
51b69a1527 SpinalHDL 1.8.0 2022-12-05 20:10:58 +01:00
Dolu1990
773f268f37 Fix FPU test syntax 2022-12-01 12:04:16 +01:00
Dolu1990
fb084327da Add VexRiscvBmbGenerator CsrPlugin withPrivilegedDebug assert 2022-11-28 16:30:47 +01:00
Dolu1990
eafeb5fe49 Add EmbeddedRiscvJtag.debugCd 2022-11-28 11:04:02 +01:00
Dolu1990
a25ae96d33 comment debug code 2022-11-21 14:02:35 +01:00
Dolu1990
572ca3fcfa Privileged debug fake maskmax to 31 2022-11-21 14:01:28 +01:00
Dolu1990
5a8cdee884 Fix CsrPlugin dcsr.stepie 2022-11-21 11:55:07 +01:00
Dolu1990
4ae7386904 Merge pull request #276 from LYWalker/master 
Add ability to debug over Intel Virtual JTAG
 2022-11-18 17:38:50 +01:00
Dolu1990
e19e59b55c Clear mprv on xretAwayFromMachine 2022-11-17 15:03:47 +01:00
Dolu1990
663174bc73 Privileged debug now implement stoptime stopcount 2022-11-17 13:58:29 +01:00
Dolu1990
36c3346e51 ensure rvc 0 is detected as a illegal instruction 2022-11-17 11:03:45 +01:00
Dolu1990
5e17ab62d6 Fix RISC-V debug hardware breakpoints 2022-11-14 14:45:11 +01:00
Dolu1990
fe68b8494e Fix a few RISC-V official debug support : 
- Disable interrupts in debug mode
- Ensure traps do not change CSR in debug mode
- step will also consider trapEvent
 2022-11-11 14:05:38 +01:00
Dolu1990
2504f9b9b9 RISC-V debug havereset implemented 2022-11-10 15:49:07 +01:00
Dolu1990
0bfaf06a4a main.cpp add VEXRISCV_JTAG=yes 2022-11-10 13:43:14 +01:00
Dolu1990
f71234786f Remove rv64 opcode (shift and lwu) 
Thanks Milan
 2022-10-27 15:44:50 +02:00
Dolu1990
d70794f252 fix regression 2022-10-27 15:38:34 +02:00
Dolu1990
5d0deb20b3 Fix regression compilation 2022-10-27 15:20:55 +02:00
Dolu1990
9f6186cd9a Add GenFullWithRiscvPrivilegedDebugJtag demo 2022-10-27 14:55:40 +02:00