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Author SHA1 Message Date
Dolu1990
2cd19c89b1 Revert unwanted push IBusDBusCachedTightlyCoupledRam 2024-04-04 10:49:48 +02:00
Dolu1990
7812bc6615 VexRiscvSmpCluster add more debug trigger options 2024-03-05 11:45:53 +01:00
Dolu1990
1943b257f2 CsrPlugin now support L1 D$ address trigger via the debugTriggersLsu option 2024-03-05 11:19:34 +01:00
Dolu1990
55566eb56f sync 2024-03-01 13:34:06 +01:00
Dolu1990
a947210d31 watchpoint improved 2024-02-28 12:29:43 +01:00
Dolu1990
8b41101a09 v1 2024-02-27 14:51:11 +01:00
Dolu1990
7723afc083 VexRiscvBmbGenerator now export IBusDBusCachedTightlyCoupledRam 2024-01-31 11:47:58 +01:00
Dolu1990
03471736e1 implement #373 IBusDBusCachedTightlyCoupledRam hexInit ramOffset args 2023-11-25 14:16:35 +01:00
Dolu1990
6734c7b0a5 Merge branch 'master' into dev 2023-11-14 11:37:16 +01:00
Dolu1990
940fb507a5 fix #376 Uncached dbus ahb, add option to ensure no combinatorial loop 2023-11-14 11:36:05 +01:00
Dolu1990
1849aa4419
Merge pull request #377 from Tectu/feature/fix-jtag 
Fix ambiguous function call to bind()
 2023-11-13 09:02:50 +01:00
Joel Bodenmann
ec31ed30cf Fix ambiguous function call to bind() 
The call to bind() can actually resolve to std::bind() instead of
libc's bind(). Ensure that we're definitely calling the correct one.
 2023-11-13 02:59:29 +01:00
Dolu1990
79e2ae248b
Merge pull request #374 from lschuermann/d/pmpold-addr-overflow 
PmpPluginOld: fix NAPOT address calculation overflow issue
 2023-11-08 15:15:05 +01:00
Dolu1990
53f79b1879
Merge pull request #375 from ekliptik/readme-verilator 
Add note about Verilator without GDB+OpenOCD
 2023-11-03 14:42:39 +01:00
Emil Tywoniak
00534dc4a8 Add note about Verilator without GDB+OpenOCD 2023-11-03 14:16:05 +01:00
Leon Schuermann
9baba6d11f PmpPluginOld: fix NAPOT address calculation overflow issue 
Because pmpaddrX registers are defined to encode the address'
[XLEN + 2 downto 2] bits, the length of a NAPOT region is defined
through the most significant 0 bit in a pmpaddrX register (which in
the case of ~0 is the 33rd non-existant "virtual" bit), and the
VexRiscv PmpOld plugin represents the addresses covered by a region as
[start; end) (bounded inclusively below and exclusively above), the
start and end address registers need to be XLEN + 4 bit wide to avoid
overflows.

If such an overflow occurs, it may be that the region does not cover
any address, an issue uncovered in the Tock LiteX + VexRiscv CI during
a PMP infrastructure redesign in the Tock OS [1].

This commit has been tested on Tock's redesigned PMP infrastructure,
and by inspecting all of the intermediate signals in the PMP address
calculation through a Verilator trace file. It works correctly for
various NAPOT and TOR addresses, and I made sure that the edge cases
of pmpaddrX = [0x00000000, 0x7FFFFFFF, 0xFFFFFFFF] are all handled.

[1]: https://github.com/tock/tock/pull/3597
 2023-11-03 09:11:42 -04:00
Dolu1990
b6f6120ec6 Merge branch 'dev' 2023-11-03 11:44:16 +01:00
Dolu1990
e71b1be8a2 demo fix 2023-11-03 11:43:59 +01:00
Dolu1990
f1d64eccc8 Fix demo 2023-11-03 11:41:16 +01:00
Dolu1990
63f1025a15 Fix demo 2023-11-03 11:41:02 +01:00
Dolu1990
4220602ba5 Merge branch 'dev' 2023-11-03 10:46:59 +01:00
Dolu1990
e6998d1cb3 Add GenFullWithOfficialRiscvDebug 2023-11-03 10:46:49 +01:00
Dolu1990
11cc9b1cf2 Add GenFullWithTcmIntegrated example 2023-11-02 12:32:19 +01:00
Dolu1990
beeec94344 Add GenFullWithTcmIntegrated example 2023-11-02 12:31:05 +01:00
Dolu1990
05df181257 Merge branch 'dev' 2023-11-02 11:59:51 +01:00
Dolu1990
0f17b395bd IBusDBusCachedTightlyCoupledRam add missing write mask 2023-11-02 11:59:33 +01:00
Dolu1990
07b0d7788b SpinalHDL 1.9.4 2023-11-01 09:42:59 +01:00
Dolu1990
a2a60bf6bc #373 Add GenFullWithTcm demo 2023-10-31 11:39:10 +01:00
Dolu1990
281818af9c #373 Add GenFullWithTcm demo 2023-10-31 11:05:00 +01:00
Dolu1990
4e051ed2a3
Merge pull request #366 from robindust-ce/master 
Add missing parameter jtagHeaderIgnoreWidth
 2023-09-26 17:39:49 +02:00
StaubRobin
960f8682ea Add missing parameter jtagHeaderIgnoreWidth 2023-09-25 22:15:50 +02:00
Dolu1990
e21dc6cda5 litex add hardwarebreapoint parameter 2023-09-20 09:08:33 +02:00
Dolu1990
acf6ad3bfd Add doc about official RISC-V debug support 2023-09-13 14:56:07 +02:00
Dolu1990
213e4b863a litex add -expose-time 2023-09-12 10:40:45 +02:00
Dolu1990
220a2733be litex privileged debug stop time now connect to clint 2023-09-08 16:47:54 +02:00
Dolu1990
ff922ec601 Merge branch 'litex-privileged-debug' into dev 2023-09-08 16:26:38 +02:00
Dolu1990
9fd127d6d9 fix naming 2023-09-08 16:26:23 +02:00
Dolu1990
73733dd8b1 litex privileged debug 2023-09-08 16:00:59 +02:00
Dolu1990
3739b9ac88 plic update 2023-08-29 08:58:48 +02:00
Dolu1990
5ef1bc775f SpinalHDL 1.9.3 2023-08-16 09:59:21 +02:00
Dolu1990
badf13be02 SpinalHDL 1.9.2 2023-08-10 09:02:15 +02:00
Dolu1990
1721ac253e SpinalHDL 1.9.0 
Merge branch 'dev'
 2023-07-21 17:45:18 +02:00
Charles Papon
fd0f23abb6 Merge branch master into dev 2023-07-11 04:19:06 +08:00
Charles Papon
1746af1cfe Fix #352 GenCustomInterrupt demo 2023-07-11 04:16:21 +08:00
Dolu1990
5860dc2321
Update DBusSimplePlugin.scala 2023-06-16 10:07:24 +01:00
Dolu1990
d95c9356fa
Merge pull request #350 from AdDraw/master 
Add cmd halfPipe function to DBusSimpleBus
 2023-06-16 07:47:40 +01:00
Dolu1990
7f647f9d8d
Update DBusSimplePlugin.scala 2023-06-16 08:47:18 +02:00
AdDraw
050b4d8c62 Add halfPipe function to DBusSimpleBus 2023-06-15 22:57:20 +02:00
Dolu1990
760a0fced5 Update SpinalHDL 2023-05-23 18:18:57 +02:00
Dolu1990
b81029f619 fix fpu underflow rounding (#343) 2023-05-16 16:50:38 +01:00