github-mirrors/VexRiscv
1
0
Fork 0
mirror of https://github.com/SpinalHDL/VexRiscv.git synced 2025-04-22 13:07:10 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions
1582 commits 39 branches 2 tags 14 MiB
Commit graph

1582 commits

This branch
This branch
All branches
Author SHA1 Message Date
Dolu1990
6289ebcbe4 Merge branch 'riscv-debug' into dev 2022-10-27 14:46:46 +02:00
Dolu1990
a6c29766da CsrPlugin now force privilegeGen when withPrivilegedDebug is enabled 2022-10-26 15:48:34 +02:00
Dolu1990
ab7b2cff3b fix diagram name 2022-10-26 10:48:21 +02:00
Dolu1990
7fd55c7851 Add VexRiscvAxi4LinuxPlicClint diagram drawio 2022-10-26 10:47:23 +02:00
Dolu1990
0e531515ac cleaning 2022-10-26 10:25:50 +02:00
Dolu1990
63dd787bce VexRiscvAxi4Linux now integrate Plic and Clint 2022-10-26 10:15:21 +02:00
Dolu1990
220af95043 Add VexRiscvAxi4Linux (untested, but generate a netlist) 2022-10-24 10:35:59 +02:00
Dolu1990
0979f8ba80 Add whitebox example 2022-10-24 10:24:41 +02:00
Dolu1990
17d52ce58f privileged debug now access data cache with caching enable 2022-10-21 18:58:40 +02:00
Dolu1990
486d17d245 CsrOpensbi now add rvc to misa 2022-10-21 18:58:13 +02:00
Dolu1990
662943522f Fix privileged debug trigger decode break logic 2022-10-21 17:21:13 +02:00
Dolu1990
95c656ceef riscv debug multiple harts 2022-10-21 12:28:17 +02:00
Dolu1990
0313f84419 Fix RISCV debug step 2022-10-20 10:36:30 +02:00
Dolu1990
4cd3f65296 Add official RISC-V debug support (WIP, but can already load / step / run code via openocd telnet) 2022-10-19 12:36:45 +02:00
Dolu1990
87c8822f55 Merge branch 'dev' (fix FPU dirty flag on csr write) 2022-10-13 09:35:55 +02:00
Dolu1990
959e48a353 Fpu now set csr status fs on FPU csr write 2022-10-06 11:13:57 +02:00
Dolu1990
7b9891829a More bus doc #266 2022-09-26 11:39:58 +02:00
Dolu1990
051d140c33 SpinalHDL 1.7.3 2022-09-19 13:27:22 +02:00
Dolu1990
fda7da00c2 add litex --wishbone-force-32b 2022-09-06 11:19:29 +02:00
Dolu1990
e3e21994b4 use SpinalHDL "dev" 2022-07-22 09:33:19 +02:00
Dolu1990
54412bde30 getDrivingReg() update 2022-07-21 09:10:26 +02:00
Dolu1990
24795ef09b SpinalHDL 1.7.1 2022-07-20 11:17:10 +02:00
Dolu1990
a650000f0b SpinalHDL 1.7.2 2022-07-11 12:03:06 +02:00
Dolu1990
b1252f47de csr opensbi now enable ebreak 2022-06-13 16:34:49 +02:00
Dolu1990
1303c0ca7c CfuPlugin.withEnable added 2022-06-09 17:57:31 +02:00
Dolu1990
1ce4c6e493 fix VexRiscvRegressionData url 2022-06-01 09:54:11 +02:00
Dolu1990
8ab9a9b12e fix VexRiscvRegressionData url 2022-06-01 09:53:41 +02:00
Dolu1990
0f6d0f022c VexRiscvBmbGenerator now also report bytesPerLine 2022-05-24 12:37:31 +02:00
Dolu1990
771eaf431e Better cache invalidation doc 2022-05-24 12:15:57 +02:00
Dolu1990
e6dfcac0be Add D$ single line flush support 2022-05-24 12:13:37 +02:00
Dolu1990
4c4913c703 Fix MPP to only retain legal values 2022-05-24 11:14:34 +02:00
Dolu1990
209fc719e8 VexRiscvBmbGenerator export more info 2022-05-24 10:19:35 +02:00
Dolu1990
48cf4120f2 Add VexRiscvSmpCluster forceMisa/forceMscratch 2022-05-23 15:49:32 +02:00
Dolu1990
0872852387 Fix DYNAMIC_TARGET / debug plugin interation corrupting the recoded next pc durring step by step #254 2022-05-17 20:44:17 +02:00
Dolu1990
b39557e226 Fix DYNAMIC_TARGET / debug plugin interation corrupting the recoded next pc durring step by step #254 2022-05-17 20:44:02 +02:00
Dolu1990
a553d3b476 Fix DYNAMIC_TARGET from triggering fetch missprediction while in debug mode #254 2022-05-17 15:27:50 +02:00
Dolu1990
8d0f7781de Fix DYNAMIC_TARGET from triggering fetch missprediction while in debug mode #254 2022-05-17 15:27:36 +02:00
Dolu1990
ba908ebada
Merge pull request #253 from mmicko/micko/riscv_formal 
Update to latest risc-v-formal
 2022-05-16 11:48:12 +02:00
Dolu1990
9c768be7af Fix CfuPlugin/VfuPlugin fork duplication 
https://github.com/google/CFU-Playground/issues/582
 2022-05-16 10:37:12 +02:00
Dolu1990
78f0a7f13e Fix CfuPlugin/VfuPlugin fork duplication 
https://github.com/google/CFU-Playground/issues/582
 2022-05-16 10:36:21 +02:00
Dolu1990
8df2dcbd40 Fix RVC step by step triggering next instruction branch predictor 2022-05-11 14:10:32 +02:00
Dolu1990
4fff62d3fe Fix RVC step by step triggering next instruction branch predictor 2022-05-11 14:10:11 +02:00
Dolu1990
e0eb00573c SpinalHDL 1.7.0a 2022-05-09 11:33:15 +02:00
Dolu1990
6326736401
Update build.sbt 2022-05-04 00:03:54 +02:00
Dolu1990
27772a65dd SpinalHDL 1.7.1 2022-04-29 15:22:34 +02:00
Dolu1990
8d6cb26421 Merge branch 'dev' 2022-04-29 15:20:29 +02:00
Dolu1990
9506b0b8f1 SpianlHDL 1.7.0 2022-04-29 14:16:41 +02:00
Dolu1990
9772e6775d
readme now document FPU / openocd limitations 2022-04-27 16:12:56 +02:00
Dolu1990
5fe1fb07d4
Merge pull request #249 from saahm/master 
Add Murax peripheral extension Tutorial
 2022-04-26 14:56:11 +02:00
Dolu1990
17007586e8 #241 Fix Murax/Briey TB timeouts 2022-04-26 11:00:40 +02:00