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Author SHA1 Message Date
Eric Matthews
659cc90605 Improved late exception support 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-02-10 11:17:01 -08:00
Eric Matthews
1b950d1586 standardized representation for rs_addr 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-02-10 11:17:01 -08:00
Eric Matthews
8271f0e4d9 accuracy improvements for simulation stats 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-02-10 11:17:01 -08:00
Eric Matthews
8033b8f113 Made CSR support optional 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-02-10 11:17:01 -08:00
Eric Matthews
330cea194e switched div-inuse logic to use phys_addr 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-02-10 11:17:01 -08:00
Eric Matthews
b038a9df7c div reuse addr fix 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-02-10 11:17:01 -08:00
Eric Matthews
f9361248ae exception speculation fix for div unit 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-02-10 11:17:01 -08:00
Eric Matthews
7dd6afd089 interface linter change 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-02-10 11:17:01 -08:00
Eric Matthews
982ce48c19 sret typo fix 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-02-10 11:17:01 -08:00
Eric Matthews
d32b35437d machine mode parameter changes 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-02-10 11:17:01 -08:00
Eric Matthews
eb1a3ab556 Made ifence optional 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-02-10 11:17:01 -08:00
Eric Matthews
a15a348ff6 renamer clean up 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-02-10 11:17:01 -08:00
Eric Matthews
f3b98e55b5 reconnect interrupts 
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
 2022-02-10 11:17:01 -08:00
Mike Thompson
baf91ea278
Rebrand as CVA5 2022-02-08 14:22:10 -05:00
Eric Matthews
6ef6aa45eb L/S exception rework 2022-01-18 11:29:35 -08:00
Eric Matthews
669b217ea0 exception updates 2022-01-18 11:29:35 -08:00
Eric Matthews
e2f162526a fence logic load-store-unit 2022-01-18 11:29:35 -08:00
Eric Matthews
c36059cbec changed uses_rs/rd to positive expressions 2022-01-18 11:29:35 -08:00
Eric Matthews
3e63a4c657 interrupt rewire 2022-01-18 11:29:35 -08:00
Eric Matthews
0b9d5dd131 rewired exception_target 2022-01-18 11:29:35 -08:00
Eric Matthews
2df4bbe5b5 switch to simple-dual-port ram 2022-01-18 11:29:35 -08:00
Eric Matthews
d1d5aa31f6 linting fix 2022-01-18 11:29:35 -08:00
Eric Matthews
ea0e798942 store queue fowarding simplification 2022-01-18 11:29:35 -08:00
Eric Matthews
32fac1116a global control signals restructuring 2022-01-18 11:29:35 -08:00
Eric Matthews
078b397c68 CSR write enable update 2022-01-18 11:29:35 -08:00
Eric Matthews
62dabe01ee rate limit retire stage when exception_pending 2022-01-18 11:29:35 -08:00
Eric Matthews
ac1b73031e added exception_unit_table 2022-01-18 11:29:35 -08:00
Eric Matthews
a52041a8e7 first stage of exception redesign 2022-01-18 11:29:35 -08:00
Eric Matthews
16daa0e1c6 register csr update 2022-01-18 11:29:35 -08:00
Eric Matthews
1c1513a48c added reset param to lfsr 2022-01-18 11:29:35 -08:00
Eric Matthews
420f7f6719 typo fixed 2022-01-18 11:29:35 -08:00
Eric Matthews
170e11296e use lutram and lfsr for FIFO 2022-01-18 11:29:35 -08:00
Eric Matthews
dec39b9041 removed old lut_ram 2022-01-18 11:29:35 -08:00
Eric Matthews
9c3f22ee65 switch spec_table to 1w_mr lutram 2022-01-18 11:29:35 -08:00
Eric Matthews
e1dbb108d5 switched toggle-mem to new lutram blocks 2022-01-18 11:29:35 -08:00
Eric Matthews
427b459eb6 new lutram components 2022-01-18 11:29:35 -08:00
Eric Matthews
17fcfa2a7b updated vendor selection config 2022-01-18 11:29:35 -08:00
Eric Matthews
d8c587f90d added registerfile bypass 2022-01-18 11:29:35 -08:00
Eric Matthews
bbbd48b799 toggle memory updates 2022-01-18 11:29:35 -08:00
Eric Matthews
fd050d8e39 replaced shift counters for clear/flush logic 2022-01-18 11:29:35 -08:00
Eric Matthews
2292cbcad5 init/clear counters changed to un-ordered 2022-01-18 11:29:35 -08:00
Eric Matthews
3cbcd3aabf delay retire by one cycle 2022-01-18 11:29:35 -08:00
Eric Matthews
c32a080294 CSR unit separated from exception logic 2022-01-18 11:29:35 -08:00
Eric Matthews
d3c5471907 prep for CSR split 2022-01-18 11:29:35 -08:00
Eric Matthews
7e0f920a12 precompute store_queue full 2022-01-18 11:29:35 -08:00
Eric Matthews
0c1634db0a moved CSR legal addr checking 2022-01-18 11:29:35 -08:00
Eric Matthews
aadeb7ed21 resolved enum conflicts 2022-01-18 11:29:35 -08:00
Eric Matthews
1b3b19e846 div control signal cleanups 2022-01-18 11:29:35 -08:00
Eric Matthews
4c3d7f025e CSR/GC restructuring 2022-01-18 11:29:35 -08:00
Eric Matthews
0ca48e42f9 CSR input cleanup 2022-01-18 11:29:35 -08:00