cva5/core
Eric Matthews b038a9df7c div reuse addr fix
Signed-off-by: Eric Matthews <ematthew@sfu.ca>
2022-02-10 11:17:01 -08:00
..
intel package import refactor 2022-01-18 11:29:35 -08:00
lutrams typo fixed 2022-01-18 11:29:35 -08:00
xilinx package import refactor 2022-01-18 11:29:35 -08:00
addr_hash.sv package import refactor 2022-01-18 11:29:35 -08:00
alu_unit.sv minor const alu changes 2022-01-18 11:29:35 -08:00
amo_alu.sv resolved enum conflicts 2022-01-18 11:29:35 -08:00
avalon_master.sv package import refactor 2022-01-18 11:29:35 -08:00
axi_master.sv package import refactor 2022-01-18 11:29:35 -08:00
axi_to_arb.sv resolved enum conflicts 2022-01-18 11:29:35 -08:00
barrel_shifter.sv package import refactor 2022-01-18 11:29:35 -08:00
binary_occupancy.sv package import refactor 2022-01-18 11:29:35 -08:00
branch_comparator.sv decode and branch cleanup 2022-01-18 11:29:35 -08:00
branch_predictor.sv linting fix 2022-01-18 11:29:35 -08:00
branch_predictor_ram.sv switch to simple-dual-port ram 2022-01-18 11:29:35 -08:00
branch_unit.sv first stage of exception redesign 2022-01-18 11:29:35 -08:00
byte_en_BRAM.sv updated vendor selection config 2022-01-18 11:29:35 -08:00
clz.sv Div improvements 2022-01-18 11:29:35 -08:00
csr_types.sv CSR input cleanup 2022-01-18 11:29:35 -08:00
csr_unit.sv exception updates 2022-01-18 11:29:35 -08:00
cycler.sv code cleanup 2018-06-11 15:24:22 -07:00
dbram.sv package import refactor 2022-01-18 11:29:35 -08:00
dcache.sv linting fix 2022-01-18 11:29:35 -08:00
ddata_bank.sv package import refactor 2022-01-18 11:29:35 -08:00
decode_and_issue.sv div reuse addr fix 2022-02-10 11:17:01 -08:00
div_core.sv div control signal cleanups 2022-01-18 11:29:35 -08:00
div_unit.sv global control signals restructuring 2022-01-18 11:29:35 -08:00
dtag_banks.sv re-parameterization 2022-01-18 11:29:35 -08:00
external_interfaces.sv l1 arbiter clean up 2022-01-18 11:29:35 -08:00
fetch.sv exception updates 2022-01-18 11:29:35 -08:00
gc_unit.sv machine mode parameter changes 2022-02-10 11:17:01 -08:00
ibram.sv package import refactor 2022-01-18 11:29:35 -08:00
icache.sv re-parameterization 2022-01-18 11:29:35 -08:00
illegal_instruction_checker.sv Made ifence optional 2022-02-10 11:17:01 -08:00
instruction_metadata_and_id_management.sv exception updates 2022-01-18 11:29:35 -08:00
interfaces.sv interface linter change 2022-02-10 11:17:01 -08:00
itag_banks.sv re-parameterization 2022-01-18 11:29:35 -08:00
l1_arbiter.sv re-parameterization 2022-01-18 11:29:35 -08:00
lfsr.sv added reset param to lfsr 2022-01-18 11:29:35 -08:00
load_queue.sv lsq interface split 2022-01-18 11:29:35 -08:00
load_store_queue.sv L/S exception rework 2022-01-18 11:29:35 -08:00
load_store_unit.sv L/S exception rework 2022-01-18 11:29:35 -08:00
mmu.sv package import refactor 2022-01-18 11:29:35 -08:00
mul_unit.sv package import refactor 2022-01-18 11:29:35 -08:00
one_hot_occupancy.sv package import refactor 2022-01-18 11:29:35 -08:00
one_hot_to_integer.sv linting fix 2022-01-18 11:29:35 -08:00
placer_randomizer.sv helper for placement randomization 2019-01-03 12:39:09 -08:00
priority_encoder.sv tool compatability changes 2022-01-18 11:29:35 -08:00
ras.sv global control signals restructuring 2022-01-18 11:29:35 -08:00
reg_inuse.sv code cleanups 2020-01-22 19:59:33 -08:00
register_bank.sv Intel inferrence changes 2022-01-18 11:29:35 -08:00
register_file.sv L/S exception rework 2022-01-18 11:29:35 -08:00
register_free_list.sv package import refactor 2022-01-18 11:29:35 -08:00
renamer.sv renamer clean up 2022-02-10 11:17:01 -08:00
riscv_types.sv interrupt rewire 2022-01-18 11:29:35 -08:00
set_clr_reg_with_rst.sv code cleanup: converted set/clr register usage into a module 2020-04-02 15:32:02 -07:00
shift_counter.sv package import refactor 2022-01-18 11:29:35 -08:00
store_queue.sv L/S exception rework 2022-01-18 11:29:35 -08:00
tag_bank.sv minor cleanups 2020-06-30 11:06:07 -07:00
taiga.sv renamer clean up 2022-02-10 11:17:01 -08:00
taiga_config.sv Made ifence optional 2022-02-10 11:17:01 -08:00
taiga_fifo.sv added reset param to lfsr 2022-01-18 11:29:35 -08:00
taiga_types.sv L/S exception rework 2022-01-18 11:29:35 -08:00
tlb_lut_ram.sv global control signals restructuring 2022-01-18 11:29:35 -08:00
toggle_memory.sv switched toggle-mem to new lutram blocks 2022-01-18 11:29:35 -08:00
toggle_memory_set.sv added reset param to lfsr 2022-01-18 11:29:35 -08:00
wishbone_master.sv package import refactor 2022-01-18 11:29:35 -08:00
writeback.sv re-parameterization 2022-01-18 11:29:35 -08:00