github-mirrors/cva6 - Blizzard Finnegan's Codeforge

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Author	SHA1	Message	Date
AngelaGonzalezMarino	eab88770ec	Altera flow support (#2649 ) Some checks are pending bender-up-to-date / bender-up-to-date (push) Waiting to run Details ci / build-riscv-tests (push) Waiting to run Details ci / execute-riscv64-tests (push) Blocked by required conditions Details ci / execute-riscv32-tests (push) Blocked by required conditions Details Integration of bitstream generation for Altera APU in general flow. * Automatic generation of IPs and sources required for Altera FPGA * Adaptation of bootrom code (UART used in Altera is different and needs a different driver) * Generation of project for Quartus Pro adding required sources and constraints - Quartus Pro licence required by users * Configuration file for openocd connection with vJTAG tap	2025-01-07 23:45:49 +01:00
AngelaGonzalezMarino	f7eb9c1e7b	Altera apu agilex7 (#2647 ) Some checks are pending bender-up-to-date / bender-up-to-date (push) Waiting to run Details ci / build-riscv-tests (push) Waiting to run Details ci / execute-riscv64-tests (push) Blocked by required conditions Details ci / execute-riscv32-tests (push) Blocked by required conditions Details This PR is adding the APU design adapted to Altera Agilex7 FPGA. It does not include integration in the Makefile nor automatic generation of Altera IPs, that will be the last PR of the Altera support.	2024-12-04 15:54:41 +01:00