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11 commits

Author SHA1 Message Date
slgth
ab2283c075
doc: keep documentation in sync with the code (#2558)
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Both the ISA and design documentations use some parameters generated from the RTL (ports, parameters).
As of now, they are committed to the repository and can be out of sync with the code.

This PR removes them from the repository and freshly generates them from the code when building HTML files.

This PR also removes prebuilt HTML files (design & ISA docs) and generates them when building the top-level Read the Docs documentation (make -C docs).
2024-10-25 12:27:09 +02:00
André Sintzoff
67a6ae966c
update riscv-isa-manual to riscv-isa-release-2c07aa2-2024-10-18 (#2560)
Since last riscv-isa-manual update (CVA6 commit 3059b1cb2):
        - Privileged Architecture 1.13 ratified
        - minor documentation changes
        - wavedrom file renamed to .edn
2024-10-22 14:44:02 +02:00
André Sintzoff
5131fb030c
doc PMP: rephrase PMP configuration description (#2540) 2024-10-11 09:12:22 +02:00
André Sintzoff
3059b1cb25
update riscv-isa-manual to riscv-isa-release-5ddbdd678-2024-08-01 (#2434)
since last riscv-isa-manual update (CVA6 commit 0bd8b8693)
2024-08-07 11:52:07 +02:00
slgth
2249202769
docs: multiple fixes (#2409) 2024-07-26 15:27:42 +02:00
slgth
3deb95af21
cv64a6_mmu: add RISC-V ISA documentation to main page (#2393) 2024-07-25 08:37:27 +02:00
JeanRochCoulon
8d413b7c54
doc PMA: cv32a65x is always idempotent and without caches (#2377) 2024-07-22 11:15:06 +00:00
JeanRochCoulon
58d490b461
Update PMP entry number from 16 to 64 (#2343) 2024-07-10 09:54:16 +00:00
André Sintzoff
51114ee0a1
machine.adoc: add missing table (#2331)
For CVA6, add table:
Encoding of A field in PMP configuration registers
2024-07-05 23:49:20 +02:00
André Sintzoff
0bd8b8693a
update riscv-isa-manual to riscv-isa-release-ebf2e3a0b-2024-07-03 (#2323)
since last riscv-isa-manual update (CVA6 commit 105d3601b):
- minor documentation changes
- use of docs-resources submodule inside riscv-isa-manual
- requires asciidoctor-lists
2024-07-05 12:06:16 +02:00
LQUA
66caecdfe6
Add RISCV documentation for cv64a6_mmu (#2315) 2024-07-03 17:24:07 +02:00