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Author SHA1 Message Date
Florian Zaruba
eaeef7da1a
verilator: Dot reference compilation issue (fix #583) (#585) 
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
 2021-01-18 14:08:06 +01:00
pawelkudlakaldec
540632a77a
dromajo_ram: Fix IEEE compliance (#584) 
According to IEEE 1800-2017 (9.2.2.4 Sequential logic always_ff procedure):

"Variables on the left-hand side of assignments within an always_ff procedure, including variables from the contents of a called function, shall not be written to by any other process."
Thus there is a proposal of changing always_ff with always because Mem_DP is driven by two processes: initial and always_ff what is forbidden.
 2021-01-18 10:36:22 +01:00
M. Tarek Ibn Ziad
d4605e3b0c
verilator: Remove static casts fixes #567 (#582) 
Static casts cause a compilation error with Verilator 4.109
 2021-01-18 10:33:39 +01:00
JeanRochCoulon
6fd1a734e0
lint: Fix synthesis tool warnings (#564) 
* Fix the lint warnings which create errors in ASIC synthesis tool:
- rs1_forwarding
- rs2_forwarding
- pmp_addr
- boot_addr
- icache_vaddr
- vaddr_to_be_flushed
- dtlb_ppn
- vaddr_vpn2_match
* mmu.sv: rename PPNW_min by PPNWMin

Signed-off-by: jcoulon <jcoulon@gemalto.com>
 2020-12-16 19:52:24 +01:00
Nils Wistoff
163eb93947 docs: add documentation for SoC 
* Memory Map
* PLIC interrupt sources

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2020-12-01 15:04:15 +01:00
André Sintzoff
296ce39211 Makefile: support spike not located in RISCV directory 2020-12-01 15:03:15 +01:00
iamywang
87426e193a pmp: Change XLEN to PLEN to fix bug in pmp_tb.sv 2020-12-01 15:00:48 +01:00
Stefan
82e7adf960
fpga/kc705: Add mcs file generation (#560) 2020-12-01 14:59:58 +01:00
Nils Wistoff
861aee01be load_unit: fix exception forwarding 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2020-12-01 14:58:45 +01:00
Nils Wistoff
a7ad3ec195 mmu: fix port width mismatch 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2020-10-07 10:01:12 +02:00
Nils Wistoff
364a11739e tb: rename tb_wt_icache to tb_cva6_icache 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2020-10-07 10:00:33 +02:00
Nils Wistoff
de5077332e cache_subsystem: merge icaches 
- add wrapper module to connect wt_icache to AXI bus
- replace std_icache by cva6_icache_axi_wrapper
- rename wt_icache to cva6_icache

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2020-10-07 10:00:33 +02:00
JeanRochCoulon
da363791d0
lint: Fix size mismatches and parameterisation (#524) 
* frontend.sv: fix lint error on icache_vaddr_q signal
* issue_stage.sv: fix lint warnings on rs1_forwarding and rs2_forwarding
signals
* load_store_unit.sv, load_unit.sv, mmu.sv, tlb.sv: fix lint warnings

Co-authored-by: jcoulon <jcoulon@gemalto.com>
 2020-10-07 09:57:58 +02:00
Moritz Schneider
7a1b214332
pmp: Fix for 32 XLEN (#537) 
* Fix wrong length PMP csrs

* Fix 32bit pmpcfg csrs
 2020-10-07 09:56:23 +02:00
Nils Wistoff
0bbc3cb5cf mmu: zero-extend paddr to match tval width 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2020-10-07 09:54:19 +02:00
Florian Zaruba
9650890a84
wt_icache: Fix for speculative accesses to NI address (#536) 
Signed-off-by: Marcelo Orenes <movera@princeton.edu>

Co-authored-by: Marcelo Orenes <movera@princeton.edu>
 2020-10-02 17:56:48 +02:00
Nils Wistoff
9de0800c0b wt_icache: remove leftover from previous simplify 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2020-10-02 14:35:58 +02:00
Nils Wistoff
6f55fb0f53 tb_wt_icache: fix icache testbench 
Minor fixes for the icache testbench to make it functional again:

- fix local imports
- adjust CachedAddrEnd to prevent an overflow of CachedRegionLength
- increase time padding between testcases
- update signal names in wave.do

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2020-09-25 13:05:10 +02:00
Nils Wistoff
a5c9931512 wt_icache: simplify FSM 
Remove redundant state from icache FSM to
- reduce code size,
- decrease ITLB miss penalty by at least one cycle.

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2020-09-25 13:04:35 +02:00
Nils Wistoff
0249cfef00 .gitmodules: change submodule url to https 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2020-09-11 18:03:49 +02:00
Nils Wistoff
3820b262e2 tb_wb_dcache: fix whitespaces and header 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2020-09-11 18:03:49 +02:00
Nils Wistoff
e82d389ea5 tb_wt_dcache: supress warn due to AXI dependency 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2020-09-11 18:03:49 +02:00
Nils Wistoff
a243d11a26 tb_wt_dcache: update dependencies 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2020-09-11 18:03:49 +02:00
Nils Wistoff
cd27cc8766 tb_wb_dcache: local imports 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2020-09-11 18:03:49 +02:00
Nils Wistoff
d59b19c2c0 add tb_wb_dcache 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2020-09-11 18:03:49 +02:00
Nils Wistoff
c6336384c4 tb_wb_dcache: add dependencies 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2020-09-11 18:03:49 +02:00
Nils Wistoff
0e066983c5 tb_read/writeport: add set and constant seq modes 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2020-09-11 18:03:49 +02:00
Nils Wistoff
2b760a2608 tb_read/writeport: minor bug fixes 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2020-09-11 18:03:49 +02:00
Nils Wistoff
adf9cfe039 tb_dcache: move shared components to 'common' 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2020-09-11 18:03:49 +02:00
Nils Wistoff
13c6ee7510 cache_ctrl: report data only for valid reads 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2020-09-11 16:53:14 +02:00
Nils Wistoff
493add1f27 cache_ctrl: do not wait for valid tag on stores 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2020-09-11 16:53:14 +02:00
Nils Wistoff
e9c1282cc1 cache_ctrl: wait for mem grant if we loose it 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2020-09-11 16:53:14 +02:00
Nils Wistoff
81b11bcfa5 cache_ctrl: req saved index while wait for tag 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2020-09-11 16:53:14 +02:00
Nils Wistoff
e058b825dc cache_ctrl: check current instead of next state 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2020-09-11 16:53:14 +02:00
Nils Wistoff
191e06c942 cache_ctrl: wait for tag_valid 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2020-09-11 16:53:14 +02:00
Nils Wistoff
f5dc8cd63f cache_ctrl: safely kill in-flight miss requests 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
 2020-09-11 16:53:14 +02:00
JeanRochCoulon
e2ff94d6ab
cva6: Make xlen configurable (#459) 
This commit adds the possibility to configure cva6 to be a 32-bit processor,
saving significant area. Currently, the 32-bit version is preliminary, it does
not yet implement the entire privileged specification. Hence it does not allow
booting Linux yet.
 2020-09-10 10:59:14 +02:00
Ruige Lee
3663eebd0a
cva6: Fix signals on the FPGA model (#513) 
Signed-off-by: Ruige Lee <295054118@qq.com>
 2020-09-08 17:00:03 +02:00
Nils Wistoff
60945b2e25 tb_wb_dcache: small bugfixes 
- update signal names in wave.do
- fix local imports
- do not invalidate memory while there is a pending read response
 2020-09-08 16:56:32 +02:00
Nils Wistoff
5618dd827f axi_intf.sv: import axi_pkg in AXI_LITE interface 2020-09-08 16:55:32 +02:00
marcosabatano
1055ccda17
cva6: Add ASIDs (#504) 
* ASID 16-BIT implementation
* merge error corrected

Signed-off-by: Marco Sabatano <marco.sabatano@hensoldt-cyber.com>
 2020-09-02 11:21:55 +02:00
Marcelo Orenes
38c08c56ec
cva6: NI/NC separation (#511) 
Signed-off-by: MARCELO ORENES VERA <movera@princeton.edu>
 2020-08-28 12:32:11 +02:00
Florian Zaruba
eef5ff6d3a
Revert "Add FPGA Optimized Register File Version" 
This reverts commit c69ebadcd2 as it unfortunately broke Linux booting
on the Genesys image.

Signed-off-by: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
 2020-08-27 18:02:42 +02:00
Shengjie Xu
6b4ddbf012
frontend: Fix tval for instruction page fault (#500) 
the second half of a 4-byte instruction split across two pages

Signed-off-by: Shengjie Xu <shengjie.xu@mail.utoronto.ca>
 2020-08-26 16:36:02 +02:00
Ruige Lee
7ba091c217
cva6: Remove global imports (#489) 
* remove global import and fix same name: is_branch
* remove the commented import statements and rename `is_branch` to `op_is_branch`

Signed-off-by: Ruige Lee <295054118@qq.com>
 2020-08-26 12:40:06 +02:00
Florian Zaruba
575cb445f8 README: Update with pointers to CVA6 
Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
 2020-08-26 11:11:14 +02:00
Emeric Poulin
8678fedda2
pmp: Fix assertion condition (#507) 
Signed-off-by: Emeric Poulin <emeric.poulin@thalesgroup.com>

Co-authored-by: Emeric Poulin <emeric.poulin@thalesgroup.com>
 2020-08-26 10:20:31 +02:00
Florian Zaruba
8de6e35288 ci: Consolidate tests 
The tests have been spread to many smaller tests previously to avoid CI timeouts.
With memory preloading the overhead of setting up the tests is dominating so we
merge the tests again.

Also remove `rv64ui-v-fence_i` from test list as it is currently failing.

Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
 2020-08-25 12:43:36 +02:00
Florian Zaruba
3a13ae0333 verilator: Add memory preloading 
Pre-load the Verilator memories through a side-band signal. We have sub-classed
the dtm_t module to prevent the debugger from pre-loading. This commit also
updates the stale bootrom.

Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
 2020-08-25 12:43:36 +02:00
Florian Zaruba
c04a73ec9d fesvr: Remove legacy repo and update Spike 
The riscv-fesvr repo has been merged with Spike. This commit removes
the legacy install and updates riscv-isa-sim to the latest version.

Signed-off-by: Florian Zaruba <florian@openhwgroup.org>
 2020-08-25 12:43:36 +02:00