This PR modifies some components in the CVA6 to fully support the WB mode of the HPDcache.
When on WB mode, there may be coherency issues between the Instruction Cache and the Data Cache. This may happen when the software writes on instruction segments (e.g. to relocate a code in memory).
This PR contains the following modifications:
The CVA6 controller module rises the flush signal to the caches when executing a fence or fence.i instruction.
The HPDcache cache subsystem translates this fence signal to a FLUSH request to the cache (when the HPDcache is in WB mode).
Add new parameters in the CVA6 configuration packages:
DcacheFlushOnInvalidate: It changes the behavior of the CVA6 controller. When this parameter is set, the controller rises the Flush signal on fence instructions.
DcacheInvalidateOnFlush: It changes the behavior of the HPDcache request adapter. When issuing a flush, it also asks the HPDcache to invalidate the cachelines.
Add additional values to the DcacheType enum: HPDCACHE_WT, HPDCACHE_WB, HPDCACHE_WT_WB
In addition, it also fixes some issues with the rvfi_mem_paddr signal from the store_buffer.
The value of the `target` matrix is currently not used by the CI.
However, it launches a job for each entry (without using it),
unnecessarily consuming CI runtime.
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
* Removing CVA6-SDK from task.yaml
* Associated PRs in task.yaml
This commit provide a new textarea to fill links to PRs used to complete the task.
* Create bug.yaml
* Update bug.yaml - Case consistency
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>
