cva6/corev_apu/fpga
AngelaGonzalezMarino eab88770ec
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Altera flow support (#2649)
Integration of bitstream generation for Altera APU in general flow.
* Automatic generation of IPs and sources required for Altera FPGA
* Adaptation of bootrom code (UART used in Altera is different and needs a different driver)
* Generation of project for Quartus Pro adding required sources and constraints - Quartus Pro licence required by users
* Configuration file for openocd connection with vJTAG tap
2025-01-07 23:45:49 +01:00
..
constraints Add support for Nexys Video board (#1925) 2024-04-04 11:13:32 +02:00
scripts Add support for Nexys Video board (#1925) 2024-04-04 11:13:32 +02:00
src Altera flow support (#2649) 2025-01-07 23:45:49 +01:00
xilinx Add support for Nexys Video board (#1925) 2024-04-04 11:13:32 +02:00
ariane-multi-hart.cfg Re-organize CVA6 and APU (#725) 2021-09-24 17:21:19 +02:00
ariane.cfg Re-organize CVA6 and APU (#725) 2021-09-24 17:21:19 +02:00
ariane_pmod.cfg Re-organize CVA6 and APU (#725) 2021-09-24 17:21:19 +02:00
ariane_pmod_tiny.cfg Re-organize CVA6 and APU (#725) 2021-09-24 17:21:19 +02:00
Makefile FPGA: Add scripts to boot linux fpga (#924) 2022-06-28 09:59:51 +02:00
sourceme.sh Add support for Nexys Video board (#1925) 2024-04-04 11:13:32 +02:00