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cva6/corev_apu/clint
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Côme bd4b57cc64
Parametrization step 3 part 3 (last) (#1940)
2024-03-18 16:19:52 +01:00
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axi_lite_interface.sv ariane_testharness/ariane_xilinx: Fix AXI ID width (#813) 2022-02-06 11:17:21 +01:00
clint.sv Parametrization step 3 part 3 (last) (#1940) 2024-03-18 16:19:52 +01:00
README.md Re-organize CVA6 and APU (#725) 2021-09-24 17:21:19 +02:00

README.md

CLINT (Core-local Interrupt Controller)

This repository contains a RISC-V privilege spec 1.11 (WIP) compatible CLINT for the Ariane Core.

The CLINT plugs into an existing AXI Bus with an AXI 4 Lite interface. The IP mirrors transaction IDs and is fully pin-compatible with the full AXI 4 interface. It does not support burst transfers (as specified in the AMBA 4 Bus specifcation)

Address Description Note
BASE + 0x0 msip Machine mode software interrupt (IPI)
BASE + 0x4000 mtimecmp Machine mode timer compare register for Hart 0
BASE + 0xBFF8 mtime Timer register