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eab88770ec
Integration of bitstream generation for Altera APU in general flow. * Automatic generation of IPs and sources required for Altera FPGA * Adaptation of bootrom code (UART used in Altera is different and needs a different driver) * Generation of project for Quartus Pro adding required sources and constraints - Quartus Pro licence required by users * Configuration file for openocd connection with vJTAG tap |
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| .. | ||
| altera | ||
| axi_mem_if@b494701501 | ||
| bootrom | ||
| clint | ||
| fpga | ||
| openpiton | ||
| register_interface@73de8e51b7 | ||
| riscv-dbg@e19d69efe7 | ||
| rv_plic@5b5c5a4c1c | ||
| src | ||
| tb | ||