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cva6/corev_apu
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Exact
Moritz Schneider b6a3aa1b03
Fix non-standard usage of SystemVerilog (#2336) 
Strings cannot be initially assigned to an integer without a cast.
2024-07-09 10:39:52 +02:00
..
axi_mem_if@b494701501 Add user field between memory and caches (#857) 2022-04-20 12:47:07 +02:00
bootrom Remove DROMAJO (#1204) 2023-04-24 23:05:53 +02:00
clint Parametrization step 3 part 3 (last) (#1940) 2024-03-18 16:19:52 +01:00
fpga Implement simple uart-based updater for the bootrom (#2267) 2024-06-19 11:24:01 +02:00
openpiton Define AXI as cva6 input parameters (#1315) 2023-07-24 10:34:30 +02:00
register_interface@73de8e51b7 Bump register interface to v0.3.1 (#819) 2022-02-10 14:19:12 +01:00
riscv-dbg@e19d69efe7 riscv-dbg: update to v0.4.1 to support 32-bit CVA6 debug (#746) 2021-10-01 17:02:34 +02:00
rv_plic@5b5c5a4c1c Bump register interface to v0.3.1 (#819) 2022-02-10 14:19:12 +01:00
src Parametrization step 3 part 3 (last) (#1940) 2024-03-18 16:19:52 +01:00
tb Fix non-standard usage of SystemVerilog (#2336) 2024-07-09 10:39:52 +02:00