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https://github.com/openhwgroup/cva6.git
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eab88770ec
Integration of bitstream generation for Altera APU in general flow. * Automatic generation of IPs and sources required for Altera FPGA * Adaptation of bootrom code (UART used in Altera is different and needs a different driver) * Generation of project for Quartus Pro adding required sources and constraints - Quartus Pro licence required by users * Configuration file for openocd connection with vJTAG tap
47 lines
1.7 KiB
INI
47 lines
1.7 KiB
INI
# * Copyright 2024 Thales AVS
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# * Copyright 2024 PlanV Technologies
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# * Copyright and related rights are licensed under the Solderpad Hardware
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# * License, Version 0.51 (the âÂÂLicenseâÂÂ); you may not use this file except in
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# * compliance with the License. You may obtain a copy of the License at
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# * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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# * or agreed to in writing, software, hardware and materials distributed under
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# * this License is distributed on an âÂÂAS ISâ BASIS, WITHOUT WARRANTIES OR
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# * CONDITIONS OF ANY KIND, either express or implied. See the License for the
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# * specific language governing permissions and limitations under the License.
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# *
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# * Author: Nicolas Levasseur, Thales AVS
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# * Additional contributions by Angela Gonzalez, PlanV Technologies
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# * Date: 8.11.2024
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# * Description: Configuration file for openocd connection
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# *
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# */
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adapter driver aji_client
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME agilex7
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}
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jtag newtap $_CHIPNAME.fpga tap -irlen 10 -expected-id 0xC341A0DD
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#0xC341A0DD
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# VJTAG ID :
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# -------------------------------------------------------
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# | 31 - 27 | 26 - 19 | 18 - 8 | 7 - 0 |
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# |-----------------------------------------------------|
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# | Node Version | Node ID | Node mfg_id | Node_inst_id |
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# -------------------------------------------------------
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# Info : node 0 idcode=00406E00 position_n=0 CVA6 core #0
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vjtag create $_CHIPNAME.fpga.tap.cva6.0 -chain-position $_CHIPNAME.fpga.tap -expected-id 0x00406E00
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target create $_CHIPNAME.cva6.0 riscv -chain-position $_CHIPNAME.fpga.tap.cva6.0 -coreid 0
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scan_chain
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init
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halt
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echo "Ready for Remote Connections"
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