docs | ||
failedtests | ||
include | ||
riscv-tests@b97a134c05 | ||
riscv-torture@6f44bec03d | ||
src | ||
tb | ||
uvm-scaffold@d59b8d6a51 | ||
.gitignore | ||
.gitlab-ci.yml | ||
.gitmodules | ||
ariane-run-torture | ||
CHANGELOG | ||
CONTRIBUTING.md | ||
LICENSE | ||
Makefile | ||
mkdocs.yml | ||
README.md | ||
src_files.yml |
Ariane RISC-V CPU
For detailed documentation refer to the online documentation (Login: zarubaf
Password: zaruba
).
Getting Started
Go and get the RISC-V tools.
Checkout the repository and initialize all submodules
git checkout git@iis-git.ee.ethz.ch:floce/ariane.git
git submodule update --init --recursive
Build Ariane by using the Makefile:
make build
Start the simulation using Modelsim:
make sim
To specify the test to run use (e.g.: you want to run rv64ui-p-sraw
inside the riscv-tests isa folder:
make sim riscv-test=rv64ui-p-sraw
If you call simc
instead of sim
it will run without the GUI.
Or start any of the unit tests by:
make dcache_arbiter
Randomized Constrained Testing with Torture
Ariane's core testbench is fully compatible with the randomized constrained testing framework called Torture. To start testing Ariane all you need is to step into the riscv-torture/
folder and issue:
make rgentest
Which will produce a single randomized program, runs it on Spike (see Getting Started) and on the RTL simulator (QuestaSim) by calling ariane-run-torture
.
Torture's overnight tests work the same way, just call
make rnight
C (a.k.a. Verilator) tests are currently not supported.
Contributing
Check out the contribution guide
Test Overview
User Mode Integer Tests
Test Name | P/V | Test Name | P/V | Test Name | P/V |
---|---|---|---|---|---|
add | ✅ ✅ | lb | ✅ ✅ | sll | ✅ ✅ |
addi | ✅ ✅ | lbu | ✅ ✅ | slli | ✅ ✅ |
addiw | ✅ ✅ | ld | ✅ ✅ | slliw | ✅ ✅ |
addw | ✅ ✅ | lh | ✅ ✅ | sllw | ✅ ✅ |
and | ✅ ✅ | lhu | ✅ ✅ | slt | ✅ ✅ |
andi | ✅ ✅ | lui | ✅ ✅ | slti | ✅ ✅ |
auipc | ✅ ✅ | lw | ✅ ✅ | sltiu | ✅ ✅ |
beq | ✅ ✅ | lwu | ✅ ✅ | sltu | ✅ ✅ |
bge | ✅ ✅ | or | ✅ ✅ | sra | ✅ ✅ |
bgeu | ✅ ✅ | ori | ✅ ✅ | srai | ✅ ✅ |
blt | ✅ ✅ | sb | ✅ ✅ | sraiw | ✅ ✅ |
bltu | ✅ ✅ | sd | ✅ ✅ | sraw | ✅ ✅ |
bne | ✅ ✅ | sh | ✅ ✅ | srl | ✅ ✅ |
sub | ✅ ✅ | simple | ✅ ✅ | srli | ✅ ✅ |
subw | ✅ ✅ | jal | ✅ ✅ | srliw | ✅ ✅ |
sw | ✅ ✅ | jalr | ✅ ✅ | srlw | ✅ ✅ |
xor | ✅ ✅ | ||||
xori | ✅ ✅ |
Compressed Instruction Tests
Test Name | P/V | Test Name | P/V | Test Name | P/V |
---|---|---|---|---|---|
rvc | ✅ ⬜ |
Machine Mode Tests
Test Name | P/F/U | Test Name | P/F/U | Test Name | P/F/U |
---|---|---|---|---|---|
csr | ✅ | illegal | ✅ | mcsr | ✅ |
breakpoint | Not Impl. | ma_addr | ✅ | ma_fetch | ✅ |
sbreak | ✅ | scall | ✅ |
Supervisor Mode Tests
Test Name | P/F/U | Test Name | P/F/U | Test Name | P/F/U |
---|---|---|---|---|---|
csr | ✅ | dirty | ✅ | ma_fetch | ✅ |
sbreak | ✅ | scall | ✅ | wfi | ✅ |