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The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
318 commits 16 branches 13 tags 288 MiB
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Florian Zaruba aa50f69434 Adapt dcache arbiter testbench using new dcache if
2017-05-29 15:51:31 +02:00
docs 📝 Updated LSU <-> D$ information 2017-05-29 11:09:59 +02:00
include Revised mem arbiter with tag valid fix issue #35 2017-05-18 12:27:50 +02:00
src Merge branch 'initial-dev' of iis-git.ee.ethz.ch:floce/ariane into initial-dev 2017-05-29 14:32:19 +02:00
tb Adapt dcache arbiter testbench using new dcache if 2017-05-29 15:51:31 +02:00
uvm-scaffold@2cefe0eae7 💚 Correct Makefile test target 2017-05-03 08:49:54 +02:00
.gitignore Adapt dcache arbiter testbench using new dcache if 2017-05-29 15:51:31 +02:00
.gitlab-ci.yml Adapt dcache arbiter testbench using new dcache if 2017-05-29 15:51:31 +02:00
.gitmodules Add UVM scaffolding submodule 2017-04-30 18:23:56 +02:00
CHANGELOG 📝 Add CHANGELOG to gitlab, manually created 2017-04-21 11:09:30 +02:00
CONTRIBUTING.md Fix issue #8 2017-05-05 11:06:37 +02:00
LICENSE 📝 Add license 2017-04-21 11:11:40 +02:00
Makefile Adapt dcache arbiter testbench using new dcache if 2017-05-29 15:51:31 +02:00
mkdocs.yml 📝 Add timing diagram for memory interface 2017-05-07 13:09:05 +02:00
README.md 📝 Added contribution guide 2017-04-20 23:06:47 +02:00

README.md

build status coverage report

Ariane RISC-V CPU

For detailed documentation refer to the online documentation (Login: zarubaf Password: zaruba).

Contributing

Check out the contribution guide