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The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
270 commits 16 branches 13 tags 288 MiB
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Florian Zaruba cc421d8fa5 Add very preliminary instruction tracer
2017-05-16 18:34:30 +02:00
docs 📝 Add pipeline diagram to diagram section 2017-05-07 23:15:10 +02:00
include Restructure IF stage 2017-05-15 18:36:31 +02:00
src Add very preliminary instruction tracer 2017-05-16 18:34:30 +02:00
tb Remove ALU signals from TB 2017-05-16 11:40:53 +02:00
test 🐛 Fixes in instruction aligner 2017-05-16 15:19:42 +02:00
uvm-scaffold@2cefe0eae7 💚 Correct Makefile test target 2017-05-03 08:49:54 +02:00
.gitignore 💚 Fixing Scoreboard testbench after #7 2017-04-28 11:57:11 +02:00
.gitlab-ci.yml ✅ Add LSU test, also to CI 2017-05-03 18:50:40 +02:00
.gitmodules Add UVM scaffolding submodule 2017-04-30 18:23:56 +02:00
CHANGELOG 📝 Add CHANGELOG to gitlab, manually created 2017-04-21 11:09:30 +02:00
CONTRIBUTING.md Fix issue #8 2017-05-05 11:06:37 +02:00
LICENSE 📝 Add license 2017-04-21 11:11:40 +02:00
Makefile Add very preliminary instruction tracer 2017-05-16 18:34:30 +02:00
mkdocs.yml 📝 Add timing diagram for memory interface 2017-05-07 13:09:05 +02:00
README.md 📝 Added contribution guide 2017-04-20 23:06:47 +02:00

README.md

build status coverage report

Ariane RISC-V CPU

For detailed documentation refer to the online documentation (Login: zarubaf Password: zaruba).

Contributing

Check out the contribution guide