cva6/core
2023-11-21 19:04:55 +01:00
..
cache_subsystem removing lint warnings.. (#1571) 2023-11-20 10:21:04 +01:00
cvxif_example verible-verilog-format: apply it on core directory (#1540) 2023-10-18 16:36:00 +02:00
frontend Code_coverage: condition RTL with the debug parameter (#1582) 2023-10-31 17:35:59 +01:00
include Spike Tandem Implementation using VCS simulator (#1561) 2023-11-09 19:29:24 +01:00
mmu_sv32 resolving lint warnings... (#1529) 2023-10-20 15:01:42 +02:00
mmu_sv39 verible-verilog-format: apply it on core directory (#1540) 2023-10-18 16:36:00 +02:00
pmp verible-verilog-format: apply it on core directory (#1540) 2023-10-18 16:36:00 +02:00
acc_dispatcher.sv verible-verilog-format: apply it on core directory (#1540) 2023-10-18 16:36:00 +02:00
alu.sv conditioned RTL with XLEN parameter (#1579) 2023-10-31 19:54:19 +01:00
amo_buffer.sv verible-verilog-format: apply it on core directory (#1540) 2023-10-18 16:36:00 +02:00
ariane_regfile.sv verible-verilog-format: apply it on core directory (#1540) 2023-10-18 16:36:00 +02:00
ariane_regfile_ff.sv verible-verilog-format: apply it on core directory (#1540) 2023-10-18 16:36:00 +02:00
ariane_regfile_fpga.sv verible-verilog-format: apply it on core directory (#1540) 2023-10-18 16:36:00 +02:00
axi_shim.sv verible-verilog-format: apply it on core directory (#1540) 2023-10-18 16:36:00 +02:00
branch_unit.sv verible-verilog-format: apply it on core directory (#1540) 2023-10-18 16:36:00 +02:00
commit_stage.sv Modify coding style to improve CC (#1642) 2023-11-21 19:04:55 +01:00
compressed_decoder.sv compressed_decoder.sv: remove useless condition (#1636) 2023-11-16 16:58:26 +01:00
controller.sv Modify coding style to improve CC (#1642) 2023-11-21 19:04:55 +01:00
csr_buffer.sv verible-verilog-format: apply it on core directory (#1540) 2023-10-18 16:36:00 +02:00
csr_regfile.sv Modify coding style to improve CC (#1642) 2023-11-21 19:04:55 +01:00
cva6.sv Spike Tandem Implementation using VCS simulator (#1561) 2023-11-09 19:29:24 +01:00
cva6_accel_first_pass_decoder_stub.sv verible-verilog-format: apply it on core directory (#1540) 2023-10-18 16:36:00 +02:00
cvxif_fu.sv resolving lint warnings... (#1529) 2023-10-20 15:01:42 +02:00
decoder.sv Spike Tandem Implementation using VCS simulator (#1561) 2023-11-09 19:29:24 +01:00
ex_stage.sv Code coverage: Add SMODE parameter to the sfence_vma instruction (#1603) 2023-11-07 15:35:06 +01:00
Flist.cva6 Add the HPDcache as cache subsystem (#1513) 2023-10-16 09:26:20 +02:00
Flist.cva6_gate Parametrize debug module (#1382) 2023-09-13 16:22:24 +02:00
fpu_wrap.sv verible-verilog-format: apply it on core directory (#1540) 2023-10-18 16:36:00 +02:00
id_stage.sv verible-verilog-format: apply it on core directory (#1540) 2023-10-18 16:36:00 +02:00
instr_realign.sv removing lint warnings.. (#1571) 2023-11-20 10:21:04 +01:00
issue_read_operands.sv Code coverage: Add SMODE parameter to the sfence_vma instruction (#1603) 2023-11-07 15:35:06 +01:00
issue_stage.sv verible-verilog-format: apply it on core directory (#1540) 2023-10-18 16:36:00 +02:00
load_store_unit.sv resolving lint warnings... (#1529) 2023-10-20 15:01:42 +02:00
load_unit.sv improve case coding style to improve CC (#1607) 2023-11-10 12:15:42 +01:00
lsu_bypass.sv verible-verilog-format: apply it on core directory (#1540) 2023-10-18 16:36:00 +02:00
mult.sv verible-verilog-format: apply it on core directory (#1540) 2023-10-18 16:36:00 +02:00
multiplier.sv verible-verilog-format: apply it on core directory (#1540) 2023-10-18 16:36:00 +02:00
perf_counters.sv perf_counters: Fix counter resetting to zero (#1546) 2023-10-19 16:24:48 +02:00
scoreboard.sv removing lint warnings.. (#1571) 2023-11-20 10:21:04 +01:00
serdiv.sv verible-verilog-format: apply it on core directory (#1540) 2023-10-18 16:36:00 +02:00
store_buffer.sv verible-verilog-format: apply it on core directory (#1540) 2023-10-18 16:36:00 +02:00
store_unit.sv removing lint warnings.. (#1571) 2023-11-20 10:21:04 +01:00