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db568f3e1d
This PR modifies some components in the CVA6 to fully support the WB mode of the HPDcache. When on WB mode, there may be coherency issues between the Instruction Cache and the Data Cache. This may happen when the software writes on instruction segments (e.g. to relocate a code in memory). This PR contains the following modifications: The CVA6 controller module rises the flush signal to the caches when executing a fence or fence.i instruction. The HPDcache cache subsystem translates this fence signal to a FLUSH request to the cache (when the HPDcache is in WB mode). Add new parameters in the CVA6 configuration packages: DcacheFlushOnInvalidate: It changes the behavior of the CVA6 controller. When this parameter is set, the controller rises the Flush signal on fence instructions. DcacheInvalidateOnFlush: It changes the behavior of the HPDcache request adapter. When issuing a flush, it also asks the HPDcache to invalidate the cachelines. Add additional values to the DcacheType enum: HPDCACHE_WT, HPDCACHE_WB, HPDCACHE_WT_WB In addition, it also fixes some issues with the rvfi_mem_paddr signal from the store_buffer. |
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| .. | ||
| dv@f0c570d112 | ||
| cov-exclude-mod.lst | ||
| cva6-simulator.yaml | ||
| cva6.hvp | ||
| cva6.py | ||
| cva6.yaml | ||
| cva6_base_testlist.yaml | ||
| cva6_spike_log_to_trace_csv.py | ||
| init_run_uvm_fsdb.do | ||
| init_run_uvm_vpd.do | ||
| init_uvm.do | ||
| Makefile | ||
| setup-env.sh | ||
| verilator_log_to_trace_csv.py | ||