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This PR modifies some components in the CVA6 to fully support the WB mode of the HPDcache. When on WB mode, there may be coherency issues between the Instruction Cache and the Data Cache. This may happen when the software writes on instruction segments (e.g. to relocate a code in memory). This PR contains the following modifications: The CVA6 controller module rises the flush signal to the caches when executing a fence or fence.i instruction. The HPDcache cache subsystem translates this fence signal to a FLUSH request to the cache (when the HPDcache is in WB mode). Add new parameters in the CVA6 configuration packages: DcacheFlushOnInvalidate: It changes the behavior of the CVA6 controller. When this parameter is set, the controller rises the Flush signal on fence instructions. DcacheInvalidateOnFlush: It changes the behavior of the HPDcache request adapter. When issuing a flush, it also asks the HPDcache to invalidate the cachelines. Add additional values to the DcacheType enum: HPDCACHE_WT, HPDCACHE_WB, HPDCACHE_WT_WB In addition, it also fixes some issues with the rvfi_mem_paddr signal from the store_buffer. |
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| bsp | ||
| core-v-verif@464bf7a0d7 | ||
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| regress | ||
| sim | ||
| tb | ||
| tests | ||
| .gitignore | ||
| README.md | ||
CVA6: Verification Environment for the CVA6 CORE-V processor core
- Directories
- Prerequisites
- Test execution
- Verification plan
- Environment variables
- 32-bit configuration
Directories:
- bsp: board support package for test-programs compiled/assembled/linked for the CVA6.
This BSP is used by both
coretestbench anduvmt_cva6UVM verification environment. - regress: scripts to install tools, test suites, CVA6 code and to execute tests
- sim: simulation environment (e.g. riscv-dv)
- tb: testbench module instancing the core
- tests: source of test cases and test lists
There are README files in each directory with additional information.
Verification plan
Verification plan is available only for vcs tool and located in sim/cva6.hvp, it's used within a modifier to filter out only needed features. Example sim/modifier_embedded.hvp for embedded config.
To generate the coverage database user should run at least a test or regression with coverage enabled by setting:
export cov=1
To view or edit verification plan use command:
cd simverdi -cov -covdir vcs_results/default/vcs.d/simv.vdb -plan cva6.hvp -mod modifier_embedded.hvp
To generate verification plan report in html format use command:
cd simurg -hvp_proj cva6_embedded -group instcov_for_score -hvp_attributes description -dir vcs_results/default/vcs.d/simv.vdb -plan cva6.hvp -mod modifier_embedded.hvp
Environment variables
Other environment variables can be set to overload default values provided in the different scripts.
The default values are:
DV_TARGET:cv64a6_imafdc_sv39DV_SIMULATORS:veri-testharness,spikeDV_TESTLISTS:../tests/testlist_riscv-tests-$DV_TARGET-p.yaml ../tests/testlist_riscv-tests-$DV_TARGET-v.yamlDV_OPTS: no default value