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Guillaume Chauvon 2ef1c1b1fc
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Update ID stage to support ZCMP, ZCMT and CVXIF with Superscalar (#2756) 
Add support for Superscalar with ZCMP, ZCMT and CVXIF.
ZCMP decoder, ZCMT decoder and CVXIF interface driver are using port 0.
Standard RVC and 32 bits instruction can take port 0 or 1.
2025-02-03 13:40:02 +01:00
..
bsp move files to a verif directory 2023-09-07 09:50:50 +02:00
core-v-verif@60e57248c4 Bump verif/core-v-verif from 19b5a3f to 60e5724 (#2724) 2025-01-22 09:11:11 +01:00
docs dvplan_csr-access.md: remove file in VerifPlans/csr_access (#2739) 2025-01-24 13:56:24 +01:00
env Fix UVM scoreboard check VLEN bits only (#2742) 2025-01-28 00:07:58 +01:00
regress Update rvfi_tracer and cva6.py (#2684) 2025-01-31 13:10:27 +01:00
sim Makefile : Add target to generate functional coverage using verdi tool (#2755) 2025-01-31 14:13:36 +01:00
tb Update ID stage to support ZCMP, ZCMT and CVXIF with Superscalar (#2756) 2025-02-03 13:40:02 +01:00
tests Update ID stage to support ZCMP, ZCMT and CVXIF with Superscalar (#2756) 2025-02-03 13:40:02 +01:00
.gitignore Convert DV into a submodule (#1591) 2023-11-03 11:20:08 +01:00
README.md Remove duplicate and out of date infos on verif readme (#2338) 2024-07-09 16:48:37 +02:00

README.md

CVA6: Verification Environment for the CVA6 CORE-V processor core

Directories:

  • bsp: board support package for test-programs compiled/assembled/linked for the CVA6. This BSP is used by both core testbench and uvmt_cva6 UVM verification environment.
  • regress: scripts to install tools, test suites, CVA6 code and to execute tests
  • sim: simulation environment (e.g. riscv-dv)
  • tb: testbench module instancing the core
  • tests: source of test cases and test lists

There are README files in each directory with additional information.

Verification plan

Verification plan is available only for vcs tool and located in sim/cva6.hvp, it's used within a modifier to filter out only needed features. Example sim/modifier_embedded.hvp for embedded config.

To generate the coverage database user should run at least a test or regression with coverage enabled by setting:

  • export cov=1

To view or edit verification plan use command:

  • cd sim
  • verdi -cov -covdir vcs_results/default/vcs.d/simv.vdb -plan cva6.hvp -mod modifier_embedded.hvp

To generate verification plan report in html format use command:

  • cd sim
  • urg -hvp_proj cva6_embedded -group instcov_for_score -hvp_attributes description -dir vcs_results/default/vcs.d/simv.vdb -plan cva6.hvp -mod modifier_embedded.hvp

Environment variables

Other environment variables can be set to overload default values provided in the different scripts.

The default values are:

  • DV_TARGET: cv64a6_imafdc_sv39
  • DV_SIMULATORS: veri-testharness,spike
  • DV_TESTLISTS: ../tests/testlist_riscv-tests-$DV_TARGET-p.yaml ../tests/testlist_riscv-tests-$DV_TARGET-v.yaml
  • DV_OPTS: no default value