mirror of
https://github.com/openhwgroup/cve2.git
synced 2025-04-24 05:57:28 -04:00
12 commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
Canberk Topal
|
53b1732b19 |
Update lowrisc_ip to lowRISC/opentitan@3a672eb36
This commit also adds memory manipulation package in ibex repository. Update code from upstream repository https://github.com/lowRISC/opentitan to revision 3a672eb36aee5942d0912a15d15055b1d21c33d6 * [mubi] Fix path in auto-gen header (Rupert Swarbrick) * [dv] Allow using memutil_dpi_scrambled even without prim_ram_1p_scr (Rupert Swarbrick) * [prim] Fix prim_ram_1p_scr Dependencies (Canberk Topal) * [dv/clk_rst_if] Split clk_rst_if jitter to 2 different values (Eitan Shapira) * [dv] Add external hjson path support in ralgen (Srikrishna Iyer) * [dv] Add sub RAL block creation knobs (Srikrishna Iyer) * [pwrmgr] Make rom_ctrl check signals multi-bit (Timothy Chen) * [dv/alert_handler] Randomize mubi input (Cindy Chen) * [flash_ctrl] Fix bank erase / info partition issue (Timothy Chen) * [ci] Fix CI failure (Weicai Yang) * [Cleanup] Remove lc_tx_e type and replace it with lc_tx_t (Weicai Yang) * [aes] Add gtech synthesis setup (Michael Schaffner) * [mubi] Enhance mubi_sync with stability check (Timothy Chen) * [prim] Fix prim_packer_fifo when ClearOnRead is false (Rupert Swarbrick) * [cleanup] Remove mubi4_e and replace it with mubi4_t (Weicai Yang) * [dv] Fix shape calculations for replicated ECC (Rupert Swarbrick) * [dv/alert] Support LPG in alert_sender/receiver pair (Cindy Chen) * [dv] Add a ReadWithIntegrity method to Ecc32MemArea (Rupert Swarbrick) * [dv] Simplify Ecc32MemArea read/write functions (Rupert Swarbrick) * [prim] Add option to not clear the packer FIFO upon read (Pirmin Vogel) * [dv] Change intg_err test from V3 to V2S (Weicai Yang) * [util] Delete generate_prim_mubi.py (Rupert Swarbrick) * [dv] Slightly generalise run_stress_all_with_rand_reset_vseq (Rupert Swarbrick) * [fpv] Fix some assumptions in prim_count (Cindy Chen) * [prim] quick path to prim_count assertion (Timothy Chen) * [dv] Support Multiple EDN Interfaces in OpenTitan (Canberk Topal) * [prim] Add xoshiro256pp primitive. (Vladimir Rozic) * [dv/prim_alert] Fix async fatal alert regression error (Cindy Chen) * [prim] Add missing include to prim_xilinx_pad_wrapper (Rupert Swarbrick) * [prim] Add missing include to prim_mubi_dec* (Rupert Swarbrick) * [dv/prim_alert_receiver] Fix assertion that consumes large mem (Cindy Chen) * [prim] Remove extra semicolon (Weicai Yang) * [chip,dv] Refactor CSR exclusion method (Srikrishna Iyer) * [top, all] update connects for mubi (Timothy Chen) * [flash_ctrl] Add plain text integrity in flash (Timothy Chen) * [prim] Add time-out functionality to prim_clock_meas (Timothy Chen) * [prim] Fix DC sythesis error (Weicai Yang) * [fpv] Fix regression failures (Cindy Chen) * [dv/ralgen] Update `dv_base_names` input from a string to a list (Cindy Chen) * [dv/ralgen] Update the `dv-base-prefix` optional input (Cindy Chen) * [doc] Add D2S and V2S checklist items to all checklists (Michael Schaffner) * [dv] Test security countermeasures (Weicai Yang) * [dv] Fix ASSERT_INIT race condition (Weicai Yang) * [syn/aes/otbn] Minor fixes to fix block level synthesis (Michael Schaffner) * [all] updated assert rtl ifdef (Timothy Chen) * [dv] Update TL intg testplan (Weicai Yang) * [prim] Add prim_fifo_async_sram_adapter to FPV list (Eunchan Kim) * [spi_device] Upload Cmd/Addr FIFO status revision (Eunchan Kim) * [dvsim] Modify resolve_branch to handle branch names with forward slash. (Todd Broch) * [prim_clock_inv] Add option to disable FPGA BUFG (Michael Schaffner) * [ralgen] Be more explicit which tool is called (Philipp Wagner) * [prim] Tweak prim_sync_reqack_data assertion so it can be disabled (Rupert Swarbrick) * [verible] Rename rule file (Philipp Wagner) * [dv/base_monitor] Cleaned up base monitor (Rasmus Madsen) * [fpv] prim_counter_fpv (Cindy Chen) * [dv/shadow_reg] Cross shadow reg error sequence with csr rw (Cindy Chen) * [dv] Fix scb multi-ral (Weicai Yang) * [dvsim] Enabling glob-style patterns for -i switch (Srikrishna Iyer) * [dv] Split sec_cm_testplan into multiple testplans (Weicai Yang) * [dv/dsim] Remove dsim's system_lib from library path (Guillermo Maturana) * [prim_packer] Resolve width mismatch (Philipp Wagner) * [prim] Fix lint error in prim_util_memload (Philipp Wagner) * [prim] Minor fix to make conn checks easy (Srikrishna Iyer) * [fpv] prim_secded FPV testbench updates bind file naming (Cindy Chen) * [dv_macros.svh] minor cleanup (Srikrishna Iyer) * [dv,xcelium] minor cleanup (Srikrishna Iyer) * [dv/shadowed_reset] Add a shadowed_rst_n interface (Cindy Chen) * [fpv] Update FPV file naming (Cindy Chen) * [top] Convert to mubi usage in some areas (Timothy Chen) * [entropy_src] mubi updates (Timothy Chen) * [prim] Add test for mubi invalid (Timothy Chen) * [prim_double_lfsr] Add duplicated LFSR primitive (Michael Schaffner) * [dv] Fix shadow reg backdoor path and enable csr_reset sequence (Weicai Yang) * [prim] Fix unused net (Timothy Chen) * [dv, clk_rst_if] Improve jitter and add scaling (Srikrishna Iyer) * [prim] Anchor buffers around register flip flops (Timothy Chen) * [alert_handler/top] Lint fixes and lc_tx_t to mubi4_t conversions (Michael Schaffner) * [prim_mubi] Replace true/false_value() functions with parameter (Michael Schaffner) * [dv/dsim] Get dsim to work at full chip (Guillermo Maturana) * [prim] Fixes for prim_count (Timothy Chen) * [top] Add various anchor points to modules (Timothy Chen) * [dv/pwrmgr] Add wakeup test sequence (Guillermo Maturana) * [reggen] Add mubi support into hjson (Timothy Chen) * [dv/shadow_reg] Fix aes shadow reg failure (Cindy Chen) * [dv/cdc] CDC simulation model (Udi Jonnalagadda) * [prim_lfsr/lint] Add temporary waiver for LOOP_VAR_OP lint error (Michael Schaffner) * [prim_clock_buf] Add lint waiver for unused parameter (Michael Schaffner) * [dvsim] Correctly set self_dir for included Hjson files (Philipp Wagner) * [util] Add tooling support for V2S milestone (Srikrishna Iyer) * [prim_mubi] Add decoder module similar to prim_lc_dec (Michael Schaffner) * [prim_mubi] Add mubi sender and sync primitives (Michael Schaffner) * [prim_mubi_pkg] Switch to True/False terminology (Michael Schaffner) * [prim] Minor work-around for xcelium (Timothy Chen) Signed-off-by: Canberk Topal <ctopal@lowrisc.org> |
||
Philipp Wagner
|
b1daf9e44e |
Update lowrisc_ip to lowRISC/opentitan@c277e3a8
Update code from upstream repository https://github.com/lowRISC/opentitan to revision 7e131447da6d5f3044666a17974e15df44f0328b Updates to Ibex code to match this import: * Include str_utils in the imported code. * List new source files in dv/uvm/core_ibex/ibex_dv.f * Update patches to resolve merge conflicts. * Update tb_cs_registers.cc and ibex_riscv_compliance.cc to match the new return code of simctrl.Exec(). Imported updates: * Do not require pyyaml >= 5.1 (Philipp Wagner) * [prim_edn_req] Forward fips signal to consumer (Pirmin Vogel) * [prim_edn_req] Use prim_sync_reqack_data primitive (Pirmin Vogel) * [prim_edn_req] De-assert EDN request if packer FIFO has data available (Pirmin Vogel) * [cleanup] Mass replace tabs with spaces (Srikrishna Iyer) * [lc_ctrl] Add script to generate the LC state based on the ECC poly (Michael Schaffner) * [dvsim] Use list for rsync command (Eunchan Kim) * [verilator] Only control the reset line when necessary (Rupert Swarbrick) * [dv/csr_utils] Add debug msg for UVM_NOT_OK err (Cindy Chen) * [dvsim] Add exclude hidden files when needed (Eunchan Kim) * [prim_sync_reqack] Add variant with associated data and optional data reg (Pirmin Vogel) * [DV, Xcelium] Fix for lowRISC/opentitan#4690 (Srikrishna Iyer) * [dvsim] Remote copy update (Srikrishna Iyer) * [prim_edn_req] Add EDN sync and packer gadget primitive (Michael Schaffner) * [prim] Add hamming code as ECC option (Timothy Chen) * [DV] Cleanup lint warnings with Verible lint (¨Srikrishna) * [prim_ram] Rearrange parity bit packing and fix wrong wmask settings (Michael Schaffner) * [lc_sync/lc_sender] Absorb flops within lc_sender (Michael Schaffner) * [prim_otp_pkg] Move prim interface constants into separate package (Michael Schaffner) * [sram_ctrl] Pull scr macro out of sram_ctrl (Michael Schaffner) * [top] Move alert handler to periphs and attach escalation clock to ibex (Michael Schaffner) * [prim_esc_rxtx/rv_core_ibex] Add default values and NMI synchronization (Michael Schaffner) * [dvsim] Fix regression publish result link with --remote switch (Cindy Chen) * [vendor/ibex] Remove duplicate check tool requirements files (Michael Schaffner) * [prim_ram_1p_scr] Fix sequencing bug in scrambling logic (Michael Schaffner) * [prim_ram*_adv] Qualify error output signals with rvalid (Michael Schaffner) * [dvsim] Fix purge not delete remote repo_top (Cindy Chen) * [lc/otp/alerts] Place size-only buffers on all multibit signals (Michael Schaffner) * [prim_buf] Add generic and Xilinx buffer primitive (Michael Schaffner) * [prim] Packer to add byte hint assertion (Eunchan Kim) * [dvsim] Logic to copy repo to scratch area (Srikrishna Iyer) * [dv/lc_ctrl] enable lc_ctrl alert_test (Cindy Chen) * [prim] documentation update for flash (Timothy Chen) * [flash_ctrl] Add additional interface support (Timothy Chen) * [dvsim] Fix publish report path (Weicai Yang) * [top_earlgrey] Instantiate LC controller in toplevel (Michael Schaffner) * [doc] Fix checklist items in V1 (Michael Schaffner) * [dv/csr_excl] Fix VCS warning (Cindy Chen) * [dv/doc] cleaned up checkist alignment (Rasmus Madsen) * [doc/dv] cleanup (Rasmus Madsen) * [dv/doc] updated dv_plan links to new location (Rasmus Madsen) * [dv/doc] changed testplan to dv_plan in markdown files (Rasmus Madsen) * [dv/doc] changed dv plan to dv doc (Rasmus Madsen) * Remove redundant ascentlint options (Olof Kindgren) * Add ascentlint default options for all cores depending on lint:common (Olof Kindgren) * [flash] documentation update (Timothy Chen) * [flash / top] Add info_sel to flash interface (Timothy Chen) * [otp] lci interface assertion related fix (Cindy Chen) * [dv/uvmdvgen] Add switch to auto-gen edn (Cindy Chen) * [util] Rejig how we load hjson configurations for dvsim.py (Rupert Swarbrick) * added changes required by sriyerg (Dawid Zimonczyk) * update riviera.hjson (Dawid Zimonczyk) * [flash_ctrl] Add high endurance region attribute (Timothy Chen) * Change VerilatorSimCtrl::Exec to handle --help properly (Rupert Swarbrick) * Simplify handling of exit_app in VerilatorSimCtrl::ParseCommandArgs (Rupert Swarbrick) * [sram_ctrl] Rtl lint fix (Michael Schaffner) * [keymgr] Add edn support (Timothy Chen) * [dv] Make width conversion explicit in dv_base_env_cfg::initialize (Rupert Swarbrick) * [dvsim] Allow dvsim.py to be run under Make (Rupert Swarbrick) * [dvsim[ rename revision_string to revision (Srikrishna Iyer) * [dvsim] Update log messages (Srikrishna Iyer) * [dvsim] fix for full verbosity (Srikrishna Iyer) * [dv] Fix Questa warning and remove unused var (Weicai Yang) * [dvsim] Add alias for --run-only (Weicai Yang) * [keymgr] Hook-up random compile time constants (Timothy Chen) * [dvsim] Add support for UVM_FULL over cmd line (Srikrishna Iyer) * [dv common] Enable DV macros in non-UVM components (Srikrishna Iyer) * [DVsim] Add support for Verilator (Srikrishna Iyer) * [DVSim] Fix how sw_images is treated (Srikrishna Iyer) * [DV common] Fixes in sim.mk for Verilator (Srikrishna Iyer) * [DV Common] Split DV test status reporting logic (Srikrishna Iyer) * [prim_arbiter_ppc] Fix lint error (Philipp Wagner) * [DV common] Factor `sim_tops` out of build_opts (Srikrishna Iyer) * [dvsim] run yapf to fix style (Weicai Yang) * [dv/common] VCS UNR flow (Weicai Yang) * [dv] Add get_max_offset function in dv_base_reg_block (Weicai Yang) * [otp_ctrl] Fix warnings from VCS (Cindy Chen) * [lint] Change unused_ waiver (Eunchan Kim) * [dv/alert_test] Add alert_test IP level automation test (Cindy Chen) * [DV] Update the was SW is built for DV (Srikrishna Iyer) * [dvsim] Replace `sw_test` with `sw_images` (Srikrishna Iyer) * [chip dv] Move sw build directory (Srikrishna Iyer) * [dv common] Update dv_utils to use str_utils_pkg (Srikrishna Iyer) * [DVSim] Method to add pre/post build/run steps (Srikrishna Iyer) Signed-off-by: Philipp Wagner <phw@lowrisc.org> |
||
Rupert Swarbrick
|
4852e307b7 |
Update lowrisc_ip to lowRISC/opentitan@e619fc60
This updates the vendored code from OpenTitan and fixes up patches as we go. The biggest change is that the support files that were in dv/data have moved to dv/tools/dvsim (with a couple of other internal renames). The icache test code also needs the corresponding path change and to rename its regression from "sanity" to "smoke" (the new name for the default regression). Update code from upstream repository https://github.com/lowRISC/opentitan to revision e619fc60c6b9c755043eba65a41dc47815612834 * [dv] Remove duplicated keys from common_sim_cfg.hjson (Rupert Swarbrick) * [dv] two small fix in dv (Cindy Chen) * [dv] Comment out example build modes from common_sim_cfg.hjson (Rupert Swarbrick) * [dv/keymgr] Cleanup some warnings in xcelium (Weicai Yang) * [lc_ctrl] Reuse an instance of the RISC-V dmi_jtag as the LC TAP (Michael Schaffner) * [otp_ctrl] Update LC types within OTP (Michael Schaffner) * [lc_ctrl] Add first cut implementation (Michael Schaffner) * [flash_ctrl] update prim flash interface (Timothy Chen) * [flash_ctrl] Add support for isolated flash partition (Timothy Chen) * [dv/common] update naming from sanity to smoke (Cindy Chen) * [prim] update naming from sanity to smoke (Cindy Chen) * [dv/base] add get_reg_by_name support in dv_base_reg_block (Cindy Chen) * [cov methodology] Functional coverage prototype (Srikrishna Iyer) * [dv] Fix tpyo (Weicai Yang) * [dv common] Wave dumping improvements / fix (Srikrishna Iyer) * [dv] Fix for `--run-only` switch (Srikrishna Iyer) * [prim_present] Add support for iterative full-round PRESENT (Michael Schaffner) * [dv] Fix VCS compile error (Weicai Yang) * [sparse-fsm-encode] Switch to Safe Rust Encoding (Sam Elliott) * [sparse-fsm-encode] Disallow Complementary Encodings (Sam Elliott) * [prim/util] Fix parameter type when using prefixes (Pirmin Vogel) * [keymgr/prim_lfsr] Correct minor errors in core files (Michael Schaffner) * [design checklist] avoid using word sanity (Cindy Chen) * [prim_lc_sync] Add two stage sync for life cycle control signals (Michael Schaffner) * [flash] update flash program to support ack / done / last (Timothy Chen) * [prim] update prim flash to have ack / done support (Timothy Chen) * Fix typo in testplan template (Rupert Swarbrick) * [dv] Fix license header for some cfg files (Weicai Yang) * [dv] Only check scoreboard from pre_abort if we were in run phase (Rupert Swarbrick) * [doc] Add lint requirements to V1 checklist (Cindy Chen) * [dv common] Minor enhancements to dv_reg_block (Srikrishna Iyer) * [dv] Fix library paths for dsim (Srikrishna Iyer) * [keymgr/dv] Update testbench (Weicai Yang) * [dv/common] Add DV_ALERT_IF_CONNECT macro (Weicai Yang) * [dv, common] Promote VCS warning to error (Srikrishna Iyer) * [prim] update clock_mux prim to avoid using BUFG (Timothy Chen) * [clkmgr] Add divider bypass during test mode (Timothy Chen) * [opt_ctrl] Change state_q assignment to ease debugging (Michael Schaffner) * [doc] Update D2 checklist and propagate updates to IPs (Michael Schaffner) * [dv/dvsim] Fix -c option compile error (Cindy Chen) * [dv] Tidy up use of get_normalized_addr (Rupert Swarbrick) * [fpv] Fix fusesoc dependecy issue (Cindy Chen) * [lint] Fix lint warning (Cindy Chen) * [dv/lint] Add new DV TB to lint batch script (Cindy Chen) * [fpv] Add lint checking to FPV tb (Cindy Chen) * [dvsim] Remove process_exports() from the code (Srikrishna Iyer) * [dvsim] Fix HJson bugs (Srikrishna Iyer) * [fpv] alert_rx/tx updates (Cindy Chen) * [prim] slicer lint fix (Eunchan Kim) * [prim] Packer to remove unused parameter. (Eunchan Kim) * [prim_lfsr] Update prim_lfsr and testbench to use correct perm width (Michael Schaffner) * [prim_lfsr] Add script to generate seed and perm constants (Michael Schaffner) * [dv/common] Upgrade some VCS warnings to errors (Weicai Yang) * [dvsim] Document and slightly improve subst_wildcards in utils.py (Rupert Swarbrick) * [csrng/dv] Initial dv environment (Steve Nelson) * [sparse-fsm-encode] Update template to prevent JG compile error (Michael Schaffner) * Gracefully shut down Verilator when software test fails (Philipp Wagner) * [otp] fix FPV compile error (Cindy Chen) * [dvsim] Kill subprocesses more gracefully (Rupert Swarbrick) * [prim] Fix Verilator lint warnings (Pirmin Vogel) * [memutil] Allocate the right number of bytes in StagedMem::GetFlat() (Rupert Swarbrick) * [memutil] Load ELF files via a staging area (Rupert Swarbrick) * [memutil] Add iterator and merging insertion interfaces to RangedMap (Rupert Swarbrick) * [memutil] Factor out "ranged map" implementation from dpi_memutil (Rupert Swarbrick) * [alert_handler] update alert hander ports (Timothy Chen) * [otp_ctrl] Update OTP output data mapping (Michael Schaffner) * [otp_ctrl] Split partition metadata into separate package (Michael Schaffner) * [prim_otp] Add TL-UL regfile for testing (sim only) (Michael Schaffner) * [memutil] Split out the non-verilator part of verilator_memutil (Rupert Swarbrick) * [dv/common] Update DV_CHECK_* macros (Weicai Yang) * [dv/common] Fix testplan path (Weicai Yang) * [prim_assert] Fixed non-UVM part of `ASSERT_ERROR (Srikrishna Iyer) * [otp_ctrl] Simplify and consolidate OTP error codes (Michael Schaffner) * [kmac] Fix critical syntax errors. (Eunchan Kim) * [dv/common] Move testplan from tools directory to data (Weicai Yang) * [dvsim] Rename verbosity wildcards to something more informative (Rupert Swarbrick) * [dv/lfsr] Update prim_lfsr_sim_cfg.hjson and add coverage (Udi Jonnalagadda) * [dv common] Added string check macros (Srikrishna Iyer) * [rtl] Use platform-agnostic log macros prim_assert (Srikrishna Iyer) * [dv] Minor fixups to dv_Utils_pkg (Srikrishna Iyer) * [dv] Fix platform-agnostic log macros (Srikrishna Iyer) * [checklist] Upgrade wording for D1 milestone (Scott Johnson) * [entropy_src/rtl] fix for dv sanity test (Mark Branstad) * [lint] Add option to bail out on first invalid Tcl cmd (Michael Schaffner) * [sram_ctrl] Add first cut implementation (Michael Schaffner) * [prim] Fix AscentLint waiver that made the tool crash (Michael Schaffner) * [checklists] Clean up and align HW and SW checklists (Michael Schaffner) * [prim] Update signal name in lint waiver rule (Pirmin Vogel) * [flash_ctrl] Switch to new keyschedule in PRINCE (Michael Schaffner) * [lint] fix the waiver format (Eunchan Kim) * [dv] Waive lint warnings in dv_macros.svh (Srikrishna Iyer) * [dv common] Add platform-agnostic log macros (Srikrishna Iyer) * [util] Add Rust Enum Support to sparse-fsm-encode.py (Sam Elliott) * [util] Add C Enum Support to sparse-fsm-encode.py (Sam Elliott) * [sparse-fsm-encode] Expand error and help messages (Michael Schaffner) * [dv/common] TLUL agent function coverage (Weicai Yang) * [dv/shadow_reg] support alert handshake checking (Cindy Chen) * [prim_present/otp_ctrl] Add round index state IOs to primitive (Michael Schaffner) * [dv] Fix 2 regression failures (Weicai Yang) * [prim_multibit_sync] Add multibit synchronizer with consistency check (Michael Schaffner) * [prim] Fix Lint warning for prim_slicer (Eunchan Kim) * [prim_generic_otp] Add TL-UL test interface stub for DV (Michael Schaffner) * [doc] Improve documentation for common_ifs (Rupert Swarbrick) * [doc] Improve pins_if block diagram (Rupert Swarbrick) * [prim_prince/present] Remove TODOs (Michael Schaffner) * [dv/common] Change TL item content when it's not accepted (Weicai Yang) * [dv/uvmgen] update has_alerts (Cindy Chen) * [dv/common] Add run opt plusarg to enable file path in the log (Weicai Yang) * [prim] Add clock buffer primitive for Xilinx FPGAs (Pirmin Vogel) * [otp_ctrl] Provision power sequencing signals (Michael Schaffner) * [dv/common] Clean up old makefile flow (Weicai Yang) * [entropy_src/rtl] review round2 changes (Mark Branstad) * [otp_ctrl] Update all FSMs to use prim_flop for the state (Michael Schaffner) * [prim_xilinx_flop] Add a Xilinx version with keep attribute (Michael Schaffner) * [prim/util] Update sparse-fsm-encode and include FSM template (Michael Schaffner) * [DV macros] minor enhancement to `DV_SPINWAIT (Srikrishna Iyer) * [DV common] Add DV_ASSERT_CTRL macro (Srikrishna Iyer) * [DV common] Enhance `DV_CHECK_MEMBER_RANDOMIZE_*` (Srikrishna Iyer) * [otbn] Use relative scope names for OTBN scopes (Rupert Swarbrick) * [verilator simutil] Add support for relative scope names to SVScoped (Rupert Swarbrick) * [fpv/prim_packer] remove assumption (Cindy Chen) * [fpv/csr_assert] support all modules for CSR assert (Cindy Chen) * [memutil] Teach verilator_memutil to load multi-segment ELF files (Rupert Swarbrick) * [memutil] Simplify how we read ELF files in verilator_memutil.cc (Rupert Swarbrick) * [memutil] Add a "verbose" flag to detail memory loads (Rupert Swarbrick) * [memutil] Parse all arguments before loading anything (Rupert Swarbrick) * [memutil] Use override keyword, not virtual for overridden method (Rupert Swarbrick) * [memutil] Use exceptions to simplify error handling (Rupert Swarbrick) * [memutil] Store the width of memory areas in bytes, not bits (Rupert Swarbrick) * [memutil] Allow memory locations to have associated LMAs (Rupert Swarbrick) * [memutil] Improve type of ElfFileToBinary in verilator_memutil.cc (Rupert Swarbrick) * [verilator simutil] Move SVScoped class into dv/verilator/cpp (Rupert Swarbrick) * [memutil] Move static functions out of VerilatorMemUtil class (Rupert Swarbrick) * [memutil] Run clang-format on verilator_memutil.* (Rupert Swarbrick) * [dv:entropy_src] Initial rng_agent and integrated into entropy_src env (Steve Nelson) * [prim_ram_adv/fpv] fix assertion (Cindy Chen) * [prim_ram_1p_scr] Simplify nonce input and align to multiples of 64b (Michael Schaffner) * [fpv/csr_assert] add csr support for regwen (Cindy Chen) * [prim*] Various lint fixes in the prims (Michael Schaffner) * [prim] remove FPV related assertions (Eunchan Kim) * [prim_lfsr] Add option to supply custom output permutation (Michael Schaffner) * [dv/common] calculate addr map size in RAL (Weicai Yang) * [flash_ctrl] Add ECC to program / erase datapaths (Timothy Chen) * [otp_ctrl] First cut implementation of the OTP controller (Michael Schaffner) * Fix invalid read in verilator_memutil (Rupert Swarbrick) * [doc] Don't strip markdown headings from HW checklist (Philipp Wagner) * [site] Set lint title (Tobias Wölfel) * [dv/prim] add basic PRINCE testbench (Udi Jonnalagadda) * [flash_ctrl] Support the notion of a 'program-repair'. (Timothy Chen) * [prim/tlul] Various small lint fixes (Michael Schaffner) * [dv/uvmdvgen] update dvsim and remove Makefile (Cindy Chen) * [util] Add script for generating sparse FSM encodings (Michael Schaffner) * [prim] Add option to register output for interrupts (Timothy Chen) * [prim_otp] First cut implementation of FPGA emulation (Michael Schaffner) * [prim_ram_1p_adv] Add 16bit ECC mode (Michael Schaffner) * [chip dv] Fix for failing GPIO test (Srikrishna Iyer) * [RTl] Generic pad wrapper default behavior fix (Srikrishna Iyer) * [slicer] Select partial from bitstream (Eunchan Kim) * [util] Don't hack __repr__ in FlowCfg (Rupert Swarbrick) * [util] Fix lint in dvsim.py (Rupert Swarbrick) * [fpv/prim_packer] Add a FPV TB (Cindy Chen) * [Keccak] Keccak_f implementation (Eunchan Kim) * [dv/csr] add common task for csr_or_field_rd_check (Cindy Chen) * [keccak] Add valid signal to random value (Eunchan Kim) * [prim] Add primitive clock divider (Timothy Chen) * [dv/shadow_reg] update sequence for storage error (Cindy Chen) * [dv/lib] clear csr_outstanding_access after reset (Cindy Chen) * [sw] Ensure Headers are Correctly Ordered (Sam Elliott) * [dv] Fix csr_rd check during reset (Weicai Yang) * Adding the first update to coverage methodology (Rasmus Madsen) * [dv] TL agent supports no clock reset (Weicai Yang) * [tlul/dv] Update test plan for tl errors (Weicai Yang) * [fpv/alert] update namings for FPV tb (Cindy Chen) * [keccak] Masked/Unmasked Keccak single round (Eunchan Kim) * [lint/prim*] Waive STAR_PORT_CONN_USE errors in generated prims (Michael Schaffner) * [prim_usb_diff_rx] Carry over wrapper for USB diff receiver (Michael Schaffner) Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org> |
||
|
Rupert Swarbrick
|
623402cf6f |
Vendor in hw/dv/{data,tools} from OpenTitan
This gets the rest of the support code needed for dvsim (which we currently duplicate). The patch: - adds the relevant directories to the vendoring file - adds a patch to rewrite some OpenTitan-specific bits - adds a "common_project_cfg.hjson" - re-runs the vendoring tool This patch won't yet change how DV code runs; we also need to redirect a couple of paths and delete dv/uvm/data for that. This will happen in the next patch. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org> |
||
|
Rupert Swarbrick
|
690f8af65e |
Update paths for vendored DV code
This commit amends some paths in the vendoring hjson file (and updates config files to use things at the new paths). Finally it re-runs the vendoring tool: Update code from upstream repository https://github.com/lowRISC/opentitan to revision 92e9242424c72c59008e267dd3779e2af5ec8e83 which just ends up with a load of file renames. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org> |
||
|
Rupert Swarbrick
|
d71aaeee06 |
Update lowrisc_ip to lowRISC/opentitan@92e92424
The shortlog from the vendor tool's automated patch is reproduced at
the bottom of this commit message.
The automated commit is squashed with one to update how we depend on
bus parameters. Before, we had to provide an "Ibex top package". This
behaved the same as OpenTitan's "lowrisc:constants:top_pkg", but
avoided having to vendor in that file.
On the OpenTitan side, this has been tidied up with commit
d266c68 ("[dv] Update dv_utils sources to use bus_params_pkg"). This
changes the dependency of dv_utils to
"lowrisc:opentitan:bus_params_pkg". We still have to provide our
own (now called "lowrisc:ibex:bus_params_pkg") and need to patch the
dv_utils dependency, but this is a bit cleaner because dv_utils is
less likely to accidentally include dependencies on OpenTitan
internals.
On our side, we have to update the vendoring patch for dv_utils (and
change its name). We also need an equivalent patch for dv_lib. Then we
rename our hacky "Ibex top package" to "bus_params_pkg". The ICache DV
environment also needs patching to use the bus parameters properly.
Phew!
* [dv] Update prim_present cov opt (Srikrishna Iyer)
* [dv] Align VCS and Xcelium cov var names (Srikrishna Iyer)
* [dv] Split coverage for functional and auto tests (Srikrishna Iyer)
* [dvsim] Do builds smartly (Srikrishna Iyer)
* [syn] Carry over synthesis flow updates from bronze (Michael
Schaffner)
* [dvsim] Lint cleanup (Srikrishna Iyer)
* [dvsim] Allow testplan to be omitted (Srikrishna Iyer)
* [dvsim] Address lowRISC/opentitan#3071 comments (Srikrishna Iyer)
* [dvsim] lint cleanup (Srikrishna Iyer)
* [dvsim] Add support for second-level indirection (Srikrishna Iyer)
* [dvsim] Change cores-root to avoid conflicts with autogen'd core
files (Michael Schaffner)
* [dvsim] Update `tests` key behavior in regressions (Srikrishna Iyer)
* [lint] Minor update of ERROR patterns in parser script (Michael
Schaffner)
* [packer] Revise the implementation (Eunchan Kim)
* [flow] Remove lint makefile (Timothy Chen)
* [flows] Various updates to tools and documents to suppose top/ip
select (Timothy Chen)
* [dv/shadow_reg] shadow_reg update error (Cindy Chen)
* [rtl/alert] change the naming from _en_i to _req_i (Cindy Chen)
* [dvsim] Tidy up config file loading in FlowCfg.py (Rupert Swarbrick)
* [dvsim] Make it simpler to derive from FlowCfg (Rupert Swarbrick)
* [lint] Update warning/error exclusions in parser scripts (Michael
Schaffner)
* [dvsim] Fix for `--tool` override (Srikrishna Iyer)
* [dvsim] Bug fix in LintCfg.py (Srikrishna Iyer)
* [prim/dv] Integrate LFSR TB with dvsim (Udi Jonnalagadda)
* [uvmdvgen] Update template to reflect bind reorg (Srikrishna Iyer)
* [dv] remove prim_lfsr_bind (Srikrishna Iyer)
* [dv] Cleanup lint warnings in csr_utils_pkg (Srikrishna Iyer)
* [dv] Cleanup lint warnings in clk_rst_if (Srikrishna Iyer)
* [dvsim] Fix coverage dashboard link (Srikrishna Iyer)
* [prim] Rename prim_util_memload.sv to svh (Philipp Wagner)
* [lint/doc] Update linting readme to reflect recent updates (Michael
Schaffner)
* [lint] Remove legacy Makefile flow for linting tools (Michael
Schaffner)
* [dvsim/lint] Enable Verilator lint in Dvsim (Michael Schaffner)
* [prim_arbiter_fixed/fpv] Add generated FPV testbench (Michael
Schaffner)
* [prim_arbiter_fixed] This adds a fixed priority arbiter (Michael
Schaffner)
* [prim] Domain-Oriented Masking AND logic (Eunchan Kim)
* [dv] Update dv_utils sources to use bus_params_pkg (Srikrishna Iyer)
* [dv] Update mem_model to use bus-params_pkg (Srikrishna Iyer)
* [dv] Update dv_lib sources to use bus_params_pkg (Srikrishna Iyer)
* [uvmdvgen] Support for setting vendor name in VLNV (Srikrishna Iyer)
|
||
|
Rupert Swarbrick
|
46ff63ad88 |
Properly vendor in mem_model from OpenTitan
This removes the manually copied version at dv/uvm/core_ibex/common and vendors things properly now that the vendor tool supports such things (this picks up the same OpenTitan version as the previous commit: lowRISC/opentitan@067272a2). |
||
|
Rupert Swarbrick
|
1dda6401c3 |
Define an Ibex-specific top_pkg core
The idea is that this can supply top_pkg.sv, a top-level thing in OpenTitan, for DV code we vendor from there. It's probably better to do this than to directly vendor in OpenTitan's top_pkg, because the latter has information about e.g. flash memory layout, which doesn't really have any meaning for Ibex. |
||
|
Rupert Swarbrick
|
8c11bd780c |
Update lowrisc_ip to lowRISC/opentitan@c91b50f3
This is manually squashed with a change to import dv_base_reg too, a new module that was created by Weicai's "csr backdoor support" patch. It's needed because it is a dependency of dv_lib. Update code from upstream repository https://github.com/lowRISC/opentitan to revision c91b50f357a76dae2ada104e397f6a91f72a33da * [prim_ram*_adv] Update core files and add prim_util dependency (Michael Schaffner) * [prim_ram*_adv] Implement Byte parity in prim_ram*_adv (Michael Schaffner) * [dvsim] Run tests in "interleaved" order (Rupert Swarbrick) * [dvsim] Remove unnecessary getattr/setattr calls from SimCfg.py (Rupert Swarbrick) * [dv] Add support for multiple ral models (Srikrishna Iyer) * [rtl] Fix prim flash dependency (Srikrishna Iyer) * [prim_fifo_sync] Make FIFO output zero when empty (Noah Moroze) * [dv] csr backdoor support (Weicai Yang) * [prim] Add a "clog2 width" function (Philipp Wagner) * [dvsim] Allow max-parallel to be set in the environment (Rupert Swarbrick) * [dvsim] Fix --reseed argument (Rupert Swarbrick) * [prim_ram/rom*_adv] Break out into individual core files (Michael Schaffner) * [prim_rom] Align port naming with prim_ram* (Michael Schaffner) * [dv] Allow a test to have "simple" timestamps (Rupert Swarbrick) * [dvsim] Improve --help message (Rupert Swarbrick) * [dvsim] Remove unused --local argument (Rupert Swarbrick) * [dvsim] Small tidy-ups to mode selection in SimCfg.py (Rupert Swarbrick) * [fpv] formal compile fix required by VC Formal (Cindy Chen) * [dvsim] Fix error detection logic in Deploy.py (Rupert Swarbrick) Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org> |
||
|
Philipp Wagner
|
8b42024cd5 |
Use vendored-in primitives from OpenTitan
Instead of using copies of primitives from OpenTitan, vendor the files in directly from OpenTitan, and use them. Benefits: - Less potential for diverging code between OpenTitan and Ibex, causing problems when importing Ibex into OT. - Use of the abstract primitives instead of the generic ones. The abstract primitives are replaced during synthesis time with target-dependent implementations. For simulation, nothing changes. For synthesis for a given target technology (e.g. a specific ASIC or FPGA technology), the primitives system can be instructed to choose optimized versions (if available). This is most relevant for the icache, which hard-coded the generic SRAM primitive before. This primitive is always implemented as registers. By using the abstract primitive (prim_ram_1p) instead, the RAMs can be replaced with memory-compiler-generated ones if necessary. There are no real draw-backs, but a couple points to be aware of: - Our ram_1p and ram_2p implementations are kept as wrapper around the primitives, since their interface deviates slightly from the one in prim_ram*. This also includes a rather unfortunate naming confusion around rvalid, which means "read data valid" in the OpenTitan advanced RAM primitives (prim_ram_1p_adv for example), but means "ack" in PULP-derived IP and in our bus implementation. - The core_ibex UVM DV doesn't use FuseSoC to generate its file list, but uses a hard-coded list in `ibex_files.f` instead. Since the dynamic primitives system requires the use of FuseSoC we need to provide a stop-gap until this file is removed. Issue #893 tracks progress on that. - Dynamic primitives depend no a not-yet-merged feature of FuseSoC (https://github.com/olofk/fusesoc/pull/391). We depend on the same functionality in OpenTitan and have instructed users to use a patched branch of FuseSoC for a long time through `python-requirements.txt`, so no action is needed for users which are either successfully interacting with the OpenTitan source code, or have followed our instructions. All other users will see a reasonably descriptive error message during a FuseSoC run. - This commit is massive, but there are no good ways to split it into bisectable, yet small, chunks. I'm sorry. Reviewers can safely ignore all code in `vendor/lowrisc_ip`, it's an import from OpenTitan. - The check_tool_requirements tooling isn't easily vendor-able from OpenTitan at the moment. I've filed https://github.com/lowRISC/opentitan/issues/2309 to get that sorted. - The LFSR primitive doesn't have a own core file, forcing us to include the catch-all `lowrisc:prim:all` core. I've filed https://github.com/lowRISC/opentitan/issues/2310 to get that sorted. |
||
|
Philipp Wagner
|
3f4e706062 |
Move Verilator simutil upstream to OpenTitan
https://github.com/lowRISC/opentitan/pull/2311 added the Verilator memutils to OpenTitan as upstream. This commit is the second part of the story, removing the code from the Ibex repository, and vendoring it back in from OpenTitan. This also superseded #844, which has now been included through OpenTitan. |
||
|
Rupert Swarbrick
|
93dd719a54 |
Merge vendor scripts for opentitan imports
This combines the existing vendor files to use the new mapping functionality added to the vendoring tool. |