16 commits

Author	SHA1	Message	Date
Robert Schilling	63666b3105	Fix some typos	2016-09-02 09:22:33 +02:00
Andreas Traber	a8987b5890	Added a basic description of the pipeline	2016-02-11 15:58:29 +01:00
Andreas Traber	6f3358adfd	Clarified hwloops with same endpoint	2016-02-11 14:10:26 +01:00
Andreas Traber	993e254947	Start adding interrupt support to simchecker	2016-02-10 10:24:49 +01:00
Andreas Traber	c39e27f3ac	Allow nested interrupts and save current value of MSTATUS to MESTATUS ... upon entering an interrupt handler	2016-02-09 09:21:26 +01:00
Andreas Traber	531745d656	Update documentation and instruction tracer for new encoding	2016-01-21 14:30:11 +01:00
Andreas Traber	1b98c11e12	Remove mscratch and change the way csr works	2015-12-26 00:15:00 +01:00
Andreas Traber	7ec2f6410f	Add LSU instructions to datasheet	2015-12-23 10:34:13 +01:00
Andreas Traber	981cd4789b	Add block diagram to titlepage	2015-12-22 16:30:42 +01:00
Andreas Traber	cfc1a17419	Add the rest of the extended alu operations	2015-12-22 16:13:20 +01:00
Andreas Traber	5a0e624be7	Add description of most alu ext operations	2015-12-22 14:32:46 +01:00
Andreas Traber	e4cbf45209	Add chapters about hardware loops and multiply-accumulate ... Add instruction specification of pulp extensions	2015-12-22 11:16:47 +01:00
Andreas Traber	dc8144a459	Added more information about debug to documentation	2015-12-21 14:54:37 +01:00
Andreas Traber	e9197db83c	Working on the documentation	2015-12-21 13:04:50 +01:00
Andreas Traber	4ed498014b	Added taken branch performance counter and excluded jumps and branches ... in icache misses	2015-12-15 18:07:32 +01:00
Andreas Traber	79bce5b31b	Add a basic datasheet for RI5CY ... Not very detailed yet, needs a lot of work still	2015-09-09 18:35:07 +02:00