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Author SHA1 Message Date
Markus Wegmann
ab812ee384 Fix further 2016-12-31 16:57:46 +01:00
Markus Wegmann
503bb05f3e Fix misaligned detection 2016-12-31 16:39:25 +01:00
Markus Wegmann
c64fbf6bf3 Fix further 2016-12-31 16:33:49 +01:00
Markus Wegmann
3d2c4336ac Fix some bug 2016-12-31 16:22:15 +01:00
Markus Wegmann
042cc85010 Fix compressed instruction logic in small prefetch buffer 
When we directly jump to an misaligned address with a C instruction, the
register cache is output, rather than the instruction memory output
 2016-12-31 15:45:05 +01:00
Markus Wegmann
0be37479b1 Fix bug in prefetcher assigning wrong input to last_address register 2016-12-30 13:53:11 +01:00
Markus Wegmann
ad4603bc40 Fix folder overwrite bug 2016-12-30 00:45:49 +01:00
Markus Wegmann
346d14c5c8 Fix some issues and cleanup 2016-12-30 00:26:15 +01:00
Markus Wegmann
caa470303e Fix system call output 2016-12-30 00:00:02 +01:00
Markus Wegmann
334e22e47f Fix 2016-12-29 23:58:02 +01:00
Markus Wegmann
2b16f8e2a6 Add report functions 2016-12-29 23:55:43 +01:00
Markus Wegmann
6a6e2022b7 Add indication which file is overwriting the config 2016-12-29 23:27:21 +01:00
Markus Wegmann
7ff400071f Add message which config is being synthesized 2016-12-29 23:22:20 +01:00
Markus Wegmann
7f17101ff6 Fix 2016-12-29 23:18:49 +01:00
Markus Wegmann
26c1b81d63 Add new synthesize method and fix synthesize_all 2016-12-29 23:15:14 +01:00
Markus Wegmann
79ea1c2920 Fix bug bug concerning folder creation 2016-12-29 23:07:25 +01:00
Markus Wegmann
cdf7a20c56 Fix bug in ri5cly-manage.py 2016-12-29 23:04:09 +01:00
Markus Wegmann
edfa9c9b41 Add synthesizeAll method to ri5cly-manage.py 2016-12-29 22:59:44 +01:00
Markus Wegmann
fe071f4af9 Implement zipping of generated core 2016-12-29 22:26:42 +01:00
Markus Wegmann
d13f0ab003 Rename hardware loop config region. Add sample configurations to script folder 2016-12-29 22:16:27 +01:00
Markus Wegmann
0ffe4f9b4f Do some cleanup in the headers 2016-12-29 22:01:39 +01:00
Markus Wegmann
3fcb6b1c9f Rename export parameter in help of ri5cly-manage.py 2016-12-29 21:48:34 +01:00
Markus Wegmann
8b69782d90 Set execute rights on ri5cly-manage.py 2016-12-29 21:43:46 +01:00
Markus Wegmann
00a2c3a8fb Create a clean code generation script for littleRISCV called ri5cly-manage.py 2016-12-29 21:41:59 +01:00
Markus Wegmann
7c99161125 Fix syntax 2016-12-28 16:33:59 +01:00
Markus Wegmann
5f0e9b2beb Fix comparator 
If-else-logic is flipped
 2016-12-28 16:32:01 +01:00
Markus Wegmann
b7365a6336 Fix simplified ALU not doing correct summand negation in each comparator case 2016-12-28 16:19:52 +01:00
Markus Wegmann
e0d92e7e4d Fix last further 2016-12-28 14:15:58 +01:00
Markus Wegmann
286d7fbe57 Fix branch in WAIT_GNT not getting processed instantly 
branch_i will not hold for more than 1 cycle (bug?), resulting in a lock
 2016-12-28 14:01:39 +01:00
Markus Wegmann
ca9d5a9ddd Try to fix bug in prefetch buffer 
When we have a branch request in WAIT_GNT, branch gets ignored. This
commit tries to fix this behaviour.
 2016-12-28 13:22:07 +01:00
Markus Wegmann
238194a233 Fix syntax of last commit 2016-12-27 17:12:47 +01:00
Markus Wegmann
2fa4e8e2c2 Add workaround for instruction memory 2016-12-27 17:10:19 +01:00
Markus Wegmann
f18096c51e Add RV32E to simchecker and tracer 2016-12-27 10:34:26 +01:00
Markus Wegmann
8426041d23 Fix syntax in debug unit 2016-12-27 09:53:17 +01:00
Markus Wegmann
8d9e8da64a Fix syntax of last 2016-12-27 09:51:01 +01:00
Markus Wegmann
a1a71c2877 Move RV32E support into parameters 2016-12-27 09:49:04 +01:00
Markus Wegmann
f19e23df33 Add to RV32E to debug unit 2016-12-27 09:34:58 +01:00
Markus Wegmann
d26747a307 RV32E support everywhere 2016-12-27 09:27:26 +01:00
Markus Wegmann
bd1ad87c43 Fix last 2016-12-26 16:31:40 +01:00
Markus Wegmann
aac3879020 Change way of RV32E implementation in register file 2016-12-26 16:16:11 +01:00
Markus Wegmann
ca07f1f552 Fix changing wrong parameter from last commit 2016-12-26 15:44:50 +01:00
Markus Wegmann
04741447d1 Add RV32E option 2016-12-26 15:39:00 +01:00
Markus Wegmann
4ffa60c2ea Try to fix syntax 2016-12-26 14:22:51 +01:00
Markus Wegmann
af1f88daf0 Try to merge comparator of ALU into adder 2016-12-26 13:41:32 +01:00
Markus Wegmann
3e198b69f0 Removed ROR and some ALU Opcodes in simplified ALU 2016-12-26 11:27:20 +01:00
Markus Wegmann
05b209473d Try to fix time loop in prefetch buffer 2016-12-24 15:27:51 +01:00
Markus Wegmann
a473a92ce8 Fix syntax and mask instruction memory address by default. 2016-12-24 15:13:29 +01:00
Markus Wegmann
3e31d75c49 Redesign small prefetch buffer for smaller area 
Add one 32 bit address register but remove comparators and one adder
 2016-12-24 15:01:46 +01:00
Markus Wegmann
bc608ecea6 Fix a bug in prefetch buffer where stall reset the address input of instruction memory 2016-12-20 14:24:07 +01:00
Markus Wegmann
a84c953cd5 Already output fetch result even if yet not ready 2016-12-20 13:23:55 +01:00