Extra bits are added alongside read/write data for the instruction and
data buses to facilitate data integrity checking.
Ibex testbench extended to generate the expected bits.
All other top-levels modified to add the new signals (which are mostly
ignored).
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
This commit adds power analysis scripts to the Arty A7
example design. They can be used by setting the newly
added `FPGAPowerAnalysis` parameter to 1.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
1-Port RAM is removed because of both execution and performance
issues. CLKIN1_PERIOD parameter is defined in clkgen module
for Vivado simulations.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
This commit updates link.ld RAM length to include max BRAM capacity
for Arty A7-35. It also changes coremark makefile to include a .vmem
output, which then can be used for FPGA implementations.
Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
This commit creates a new top level wrapping the core, register file and
icache RAMs. The tracing top level is also renamed to ibex_top_tracing
to match. This new top level is intended to enable a dual core lockstep
implementation of Ibex.
There are no functional changes in this commit, only wiring.
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
The documentation restructure in #1119 resulted in a new URL for the
documentation on Ibex system examples. This commit updates the in-tree
link to reference that new URL.
Signed-off-by: Alex Bradbury <asb@lowrisc.org>
This commit makes sure that whenever Vivado is used, the Verilog
define `FPGA_XILINX` is set. This define can be used to enable Xilinx
specific pragmas in the RTL code. It is currently used to implement
the performance counters with DSP slices (incl. integrated output
registers for counter widths <= 32) which helps to save logic resources
and FFs (-7% and -15% when using e.g. 10 counters).
Previously, we had to set this parameter in every single top-level .core
file using Ibex.
Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
- Add a major and minor alert output which can be used by the system to
react to fault injection attacks
Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
Use Xilinx-specific implementations for primitives, such as RAM and the
clock gate (which will now be implemented using a BUFGCE macro, and no
longer with a latch).
Verified in Vivado synthesis to pick up the Xilinx primitive now.
