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Rupert Swarbrick
b66f199151 Update lowrisc_ip to lowRISC/opentitan@ad629e3e6 
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
ad629e3e6e70c5eaa3c2dd68457b0a020448b35f

* [dvsim] Introduce {self_dir} as variable (Philipp Wagner)
* [dvsim] Small cleanups (Philipp Wagner)
* [prim_lfsr] Minor lint fix (Michael Schaffner)
* [dv] Update sec_cm testplan (Weicai Yang)
* [prim/lint] Move waiver to correct waiver file (Michael Schaffner)
* [prim_assert] Relocate waivers to dedicated prim_assert.waiver file
  (Michael Schaffner)
* [alert_handler] Lint fixes and waiver updates (Michael Schaffner)
* [prim_lc_receiver] Add parameter to select reset value (Michael
  Schaffner)
* [lint] Add lint waiver for IP regfiles with shadow resets (Michael
  Schaffner)
* [fpv] Fix Verible lint errors (Philipp Wagner)
* [prim_lfsr] Minor lint fixes (Timothy Chen)
* [clkmgr] Fix measurement control CDC (Timothy Chen)
* [fpv/prim_counter] Pad one bit to include overflow case (Cindy Chen)
* [fpv] Fix issue lowRISC#8371 (Zeeshan Rafique)
* [flash_ctrl] Flash ctrl security hardening (Timothy Chen)
* [dv] Fix CI error (Cindy Chen)
* [prim_alert_*] Extend SVAs for FPV (Michael Schaffner)
* [prim_alert_*] Update DV TB to respect initialization timing
  (Michael Schaffner)
* [prim_alert_rxtx_fpv] Update FPV environment and fix SVAs (Michael
  Schaffner)
* [prim_alert_sender] Update sender to support in-band reset mechanism
  (Michael Schaffner)
* [prim_alert_sender] Simplify sender and clear ping req upon sigint
  (Michael Schaffner)
* [prim_lc_sender] Add option to select reset value (Michael
  Schaffner)
* [prim] Correct assertion valid term (Timothy Chen)
* [prim_lc_combine] Align behavior of lc combine with mubi functions
  (Michael Schaffner)
* [fpv/tool] Support GUI mode on dvsim (Cindy Chen)
* [prim_lfsr] Further permutation refinements for SBox layer (Michael
  Schaffner)
* [dv/shadow_reg] Shadow register write by field (Cindy Chen)
* [prim] Fix the edge type (Eunchan Kim)
* [checklist] Updates to checklist for D2 status (Tom Roberts)
* [prim_mubi_pkg] Add a generic multibit type and associated functions
  (Michael Schaffner)
* [prim] Minor fix and clarification to prim_count (Timothy Chen)
* [keymgr/dv] Update testplan and covergroup plan (Weicai Yang)
* [prim_lc_combine] Fix parameterization error (Michael Schaffner)
* [fpv/prim_count] Small update on prim_count assertions (Cindy Chen)
* [dv] Add ip_name in reg_block (Weicai Yang)
* [keymgr] Finalize keymgr hardening (Timothy Chen)
* [prim_lc_combine] Add a prim to compute logical AND/OR for LC
  signals (Michael Schaffner)
* [dv] Remove common_cov_excl.el from unr.cfg (Weicai Yang)
* [dv/top_level] Loop through the SW test multiple times (Cindy Chen)
* [flash_ctrl] Various clean-up and updates (Timothy Chen)
* [prim] Change prim_reg_cdc assertions (Timothy Chen)
* [prim, keymgr] Migrate keymgr_cnt to prim_count (Timothy Chen)
* [sw dv] Multi-site support for Verilator (Martin Lueker-Boden)
* [dv/csr] Update write exclusion wdata value (Cindy Chen)
* [dv/dv_base_reg] remove debug display (Cindy Chen)
* [dv/shadow_reg] Fix alert shadow_reg regression error (Cindy Chen)
* [top] Integrate ast into fpga (Timothy Chen)
* [prim_lfsr] Improve statistics of non-linear output (Michael
  Schaffner)
* [prim_esc_receiver] Fix response toggling corner case (Michael
  Schaffner)
* option to use partner ast_pkg (Sharon Topaz)
* [dv/prim_esc] Double the ping timeout cycles (Cindy Chen)
* [dv] Use sed to add -elfile for each excl file (Weicai Yang)
* [dv] Fix coverage report error (Weicai Yang)
* [dv] Update common exclusion file (Weicai Yang)
* [dv/prim_esc] Improve FSM coverage (Cindy Chen)
* [reggen] Add a check to limit the swaccess type for shadow regs
  (Michael Schaffner)
* [prim_subreg_shadow] Fix for W1S/W0C corner case (Michael Schaffner)
* [prim_subreg_shadow] Disallow phase updates when storage err is
  present (Michael Schaffner)
* [dvsim] Add passing count by milestone in reports (Srikrishna Iyer)
* [dv/tool] Include toggle coverage for prim_alert_sender in
  cover_reg_top (Cindy Chen)
* [clkmgr] Harden clock manager through frequency measurements
  (Timothy Chen)
* [dv] Only enable VCS -kdb when dumping waves (Weicai Yang)
* [dv] Fix shadow reg (Weicai Yang)
* [dvsim] Allow non-integral values of --reseed-multiplier (Rupert
  Swarbrick)
* [ast] Fixes for various ast issues (Timothy Chen)
* [prim_esc_receiver] Assert escalation in case of sigint error
  (Michael Schaffner)
* [prim_esc_receiver] Minor signal renaming for consistency (Michael
  Schaffner)
* [dv/alert_handler] Support shadow register sequence (Cindy Chen)
* [verilator] Use FileSz rather than MemSz when flattening ELF files
  (Michael Munday)
* [prim_subreg_shadow] Only assert QE when committed_reg is written
  (Michael Schaffner)
* [dv,verilator] Round up SV_MEM_WIDTH_BYTES to a multiple of 4
  (Rupert Swarbrick)
* [prim] Add missing include (Pirmin Vogel)
* [dv/cover_cfg] Exclude prim_alert/esc from xcelium (Cindy Chen)
* [dv/cover_cfg] Exclude prim_alert/esc pairs (Cindy Chen)
* [clkmgr] Use local BUFHCE clock gates on FPGA (Pirmin Vogel)
* [prim_prince] Mark "leaf" functions in prince_ref.h as static inline
  (Rupert Swarbrick)
* [dv/shadow_reg] Check status after shadow_reg write (Cindy Chen)
* [dv/shadwo_reg] Shadow reg common sequence update (Cindy Chen)
* [otp_ctrl/lc_ctrl] Add 32bit OTP vendor test ctrl/status regs to LC
  TAP (Michael Schaffner)
* [otp_ctrl] Add VENDOR_TEST partition (Michael Schaffner)
* [prim] Edge Detector (Eunchan Kim)
* [prim_diff_decode] Fix asynchronous assertions (Michael Schaffner)
* [spi_device] Instantiate Upload module (Eunchan Kim)
* [dv] Add sv_flist_gen_flags HJson var for FuseSoc (Srikrishna Iyer)
* [dv, xcelium] Properly pass excl files to IMC (Srikrishna Iyer)
* [reg] Fix shadow reg update during storage error (Timothy Chen)
* [regfile] Refactor cdc handling to the reg level (Timothy Chen)
* [dv/prim_esc] Add a testplan and increase coverage (Cindy Chen)
* [dv] Update TLUL and EDN frequency (Weicai Yang)
* [rstmgr, top] Add support for shadow resets (Timothy Chen)
* [dv] Update Xcelium cover ccf (Srikrishna Iyer)
* [dv] reduce seeds for CSR tests (Weicai Yang)
* [usb/top] Remove AND gates on non-AON domain and rename 3.3V signal
  (Michael Schaffner)
* [dv/prim_alert] Improvement on prim_alert tb (Cindy Chen)
* [prim] FIFO SRAM Adapter fix (Eunchan Kim)
* [prim] Add Write Mask port (Eunchan Kim)
* [dv] Fix timescale issue with Xcelium (Weicai Yang)
* [dv/prim_esc] Fix prim_esc regression error (Cindy Chen)
* [dv/dv_base_reg] change from uvm_low to uvm_high (Cindy Chen)
* [sram_ctrl] Harden initialization counter (Michael Schaffner)
* [tools/uvmdvgen] Fix path in testplan inclusion (Guillermo Maturana)
* [dv] Change stress_all_with_rand_reset to V3 (Weicai Yang)
* [dv] fix tl error coverage (Weicai Yang)
* [dv] Add macro DV_GET_ENUM_PLUSARG (Weicai Yang)
* [prim] SRAM Async FIFO (Eunchan Kim)
* [dv, xcelium] Fix statement coverage extraction (Srikrishna Iyer)
* [dvsim] Minor fixes to coverage extraction (Srikrishna Iyer)
* [prim_lfsr] Do not shadow |state| variable (Philipp Wagner)
* [prim] Add non-linear out option to prim_lfsr (Timothy Chen)
* [dv] Constrain TLUL to 24Mhz or higher (Weicai Yang)
* [primgen] Instantiate tech libs in stable order (Philipp Wagner)
* [primgen] Actually find the Verible Python wrapper (Philipp Wagner)
* [dv/prim_esc] fix regression error (Cindy Chen)
* [dv] Fix shadow reg predict (Weicai Yang)
* [dv/common] Exclude assertion coverage from IP level testbench
  (Cindy Chen)
* [dv/prince] hit additional toggle coverpoints (Udi Jonnalagadda)
* [sram_ctrl] Update docs (Michael Schaffner)
* [sram_ctrl] Absorb prim_ram_1p_scr (Michael Schaffner)
* [dv/prim_alert/esc] Improvements for prim_alert/esc_tb (Cindy Chen)
* [dv/dvsim] Add "testfile" grading option (Guillermo Maturana)
* [dv/prim_esc] Direct test for prim_rx/tx (Cindy Chen)
* [dv/utils] added 6MHz to clk_freq_mhz_e (Dror Kabely)
* [prim_xor2/lint] Add waiver for .* use in generated prim (Michael
  Schaffner)
* [dv, doc] Replace all 'dv.plan' with testplan (Srikrishna Iyer)
* Fix the testplan link in dvsim code (Srikrishna Iyer)
* [dv/dsim] Add dsim workaround for issue 242 (Guillermo Maturana)
* [util, reggen] Support standardized cdc handling for regfile
  (Timothy Chen)
* [dv/shadow_reg] Align shadow_reg field update behavior (Cindy Chen)
* [dvsim] Fix publish report summary typo (Cindy Chen)
* [rtl/prim_alert_sender] Allow ping_req to stay high without error
  (Cindy Chen)
* [dvsim] Separate publish report from dvsim flow [PART3] (Cindy Chen)
* [dv/prim_alert] Add a testbench for prim_alert (Cindy Chen)
* [otp_ctrl] Connect test-related GPIO signal (Michael Schaffner)
* [prim_subreg_shadow] Make local parameter a localparam (Philipp
  Wagner)
* [prim_subreg] Make software access type an enum (Philipp Wagner)
* [rtl/prim_diff_decode] Add prim_flop_2sync dependency (Cindy Chen)
* [otp_ctrl] Update AscentLint waiver file (Michael Schaffner)
* [edn] Add MaxLatency assertion (Eunchan Kim)
* [prim_subreg_shadow] Correct write data signal usage (Michael
  Schaffner)
* [script/dvsim] Separate publish report from dvsim flow [PART2]
  (Cindy Chen)
* [prim_lfsr] Fix assertion issue occuring right after reset (Michael
  Schaffner)
* [dv/shadow_reg] Handle CSR automated sequence write abort (Cindy
  Chen)
* [dv/dv_lib] Add post_apply_reset for extra delay (Guillermo
  Maturana)
* [dv] Add function coverage plan for tl_errors, tl_intg_err (Weicai
  Yang)
* [dv] Remove tl_intg_err in top-level and increase seeds for
  tl_intg_err (Weicai Yang)
* [dv/shadow_reg] Fix alert shadow reg regression error (Cindy Chen)

Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
 2021-11-16 10:49:23 +00:00
Greg Chadwick
e70add7228 [ci] Add co-simulation testing of CoreMark 2021-11-12 09:39:38 +00:00
Greg Chadwick
63ac629d10 [coremark] Add option to coremark build to suppress pcount dump 
When using cosim checking performance counters won't match between ISS
and RTL. This option allows coremark to be run under cosim checking.
 2021-11-12 09:39:38 +00:00
Greg Chadwick
c3dd66e9fa [cosim] Update documentation for cosim 
Also adjusts quick install instructions to use /opt/spike-cosim as
that's the path used by the pre-packaged version.
 2021-11-12 09:39:38 +00:00
Greg Chadwick
84d2d6ad3f [cosim] Add Simple System with cosim 2021-11-12 09:39:38 +00:00
Greg Chadwick
580ddaad13 [simple_system] Refactor Simple System 
Refactor Simple System into a C++ class. This enables easy extension of
Simple System.
 2021-11-12 09:39:38 +00:00
Greg Chadwick
b57cad5387 [dv] Add matched instruction count to cosim 2021-11-12 09:39:38 +00:00
Greg Chadwick
c10b56ed17 [dv] Adjust cosim include paths 
Some Spike include files can clash with libelf include files. Avoid
directly adding riscv and fesvr directories to include path to prevent
this.
 2021-11-12 09:39:38 +00:00
Michael Munday
c35472abb9 [bitmanip][zba] Add support for Zba (address calculation) extension 
Add support for the Zba extension added in v0.93 of the bit manipulation
specification (unchanged in v1.0.0). The new instructions added are:

  - sh1add: rd = (rs1 << 1) + rs2
  - sh2add: rd = (rs1 << 2) + rs2
  - sh3add: rd = (rs1 << 3) + rs2

The instructions are single cycle and have been implemented using the
adder in the ALU.

Signed-off-by: Michael Munday <mike.munday@lowrisc.org>
 2021-11-01 09:58:01 +00:00
Miguel Escobar
d1aff2f1a4 [dv] get ibex dv co-sim to run w questa 
This resolves lowRISC/Ibex#1280.
 2021-10-25 19:47:07 +02:00
Tom Roberts
cfeef7e864 [doc] Update DIT documentation for unaligned ld/st 
Relates to #1414

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
 2021-10-19 14:06:53 +01:00
Henner Zeller
a345da3bad Change use of blocking assignment to non-blocking inside always_ff 
Fixes #1457

Signed-off-by: Henner Zeller <h.zeller@acm.org>
 2021-10-16 16:46:34 +01:00
Greg Chadwick
416ecb10df [dv] Add co-simulation environment support to UVM testbench 2021-10-15 11:30:35 +01:00
Greg Chadwick
c03cc91a5d [rtl] RVFI changes and extensions for co-simulation 
This adds some new `rvfi_ext` signals that are needed by the
co-simulation environment.

It also fixes/alters `rvfi_trap`. Previously it wouldn't work correctly
in various cases. Now it is fully functional, though it's meaning
includes more trap cases than the RVFI spec strictly includes. It is now
set for any instruction that produces a synchronous trap (everything bar
interrupts).
 2021-10-15 11:30:35 +01:00
Greg Chadwick
648fadb34a [dv] Add co-simulation framework 2021-10-15 11:30:35 +01:00
Greg Chadwick
f4e3eefcfb [rtl,dv,doc] Flip priority of fast interrupts 
This matches the priority used in Spike.

This also fixes an issue in the DV where the priority of
external/software/timer interrupts wasn't calculated correctly.
 2021-10-15 11:30:35 +01:00
Udi
ff6797b26f [ibex/ml] add CSR/mem_error tests to ml_testlist 
Signed-off-by: Udi <udij@google.com>
 2021-10-07 16:54:46 -07:00
Zachary Snow
0aa02b0f3f [syn] Use read_verilog -defer in yosys_run_synth.tcl 
Newer versions of sv2v carry through elaboration system tasks like
$fatal. ibex_top_tracing uses $fatal, but isn't actually used in the
syn_yosys flow. By using -defer, unused modules like ibex_top_tracing
are not elaborated in Yosys.
 2021-10-07 12:29:16 +01:00
zeeshanrafique23
873e2281cf remove unused RD in branch insn from tracer 2021-10-01 17:51:18 +01:00
Rupert Swarbrick
305f0a80ea Add missing parameters to ibex_top_tracing 2021-09-27 11:06:04 +01:00
Wojciech Sipak
45f727dfc6 set verible action version to 'main' 2021-09-23 11:55:50 +01:00
Wojciech Sipak
ac8934459b bump verible action version 2021-09-21 16:22:17 +01:00
Greg Chadwick
31b2f6c863 [rtl] Fix retired instruction counters 
When the writeback stage is present the retired instruction counter
(minstret) and the retired compressed instruction counter could see an
off by one error when an instruction was in the writeback stage when
reading the counters. With this fix the ID stage observes the
incremented value of the counters when an instruction that would
increment them is in writeback.
 2021-09-17 12:28:10 +01:00
Greg Chadwick
75c030b776 [rtl] Factor ID exceptions into instruction kill 
Without this an instruction taking an exception will enter WB whilst
simultaneously remaining in ID. This didn't cause any known functional
issues as in the scenarios it occurred the RF write was disabled and the
WB stage eventually gets flushed. However it's still bad behaviour and
could lead to functional issues when RTL changes. It also eases the
co-simulation DV implementation.
 2021-09-17 12:28:10 +01:00
Wojciech Sipak
31c5b5eefd [ci] Add GHA workflows to review PRs using Verible 
Any activity regarding a Pull Request will trigger
workflows that create automatic code review
using outputs from Verible linter
 2021-09-16 12:40:25 +02:00
Greg Chadwick
6cbd7d21c5 [dv] Fix transaction ordering in ibex_mem_intf_monitor 
Previously the monitor would emit write transactions the cycle the
request is seen and emit read transactions the cycle the response is
seen. This allowed later write transactions to be emitted before earlier
reads (where a new write transaction is started the cycle a read
response returns).

Now both read and write transactions are emitted when their response is
seen.

In addition the error field from the response is copied into the
transaction.
 2021-09-01 09:43:37 +01:00
Greg Chadwick
6815e7b714 [rtl] Implement mvendorid/marchid/mimpid CSRs 2021-08-31 17:39:01 +01:00
Philipp Wagner
b99da424ff [style] Indent package bodies 
The style guide requires the package body to be indented with two
spaces.
 2021-08-31 15:30:28 +02:00
Philipp Wagner
a25790abf9 [style] Indent module header with two spaces 
Both the parameter and the port list in a module header should be
indented with two spaces, according to our style guide.
 2021-08-31 15:30:28 +02:00
Philipp Wagner
87bcd13a12 [style] Use logical operators for reset 2021-08-31 15:30:28 +02:00
Philipp Wagner
be27bc8bcf [style] Fix whitespace issues around operators 
Our style guide typically require a single whitespace around operators.
 2021-08-31 15:30:28 +02:00
Philipp Wagner
b5011ecec6 [style] Format module instantiations in tabular format 
The style guide mandates tabular format in port expressions in module
instantiations
(https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md#module-instantiation).

The style guide also mandates a two-space indentation for ports and
parameters in module instantiations.

Apply the formatting produced by verible-format to match our style
guide.
 2021-08-31 15:30:28 +02:00
Tom Roberts
48f11c6733 [rtl] Add bus integrity checking 
Extra bits are added alongside read/write data for the instruction and
data buses to facilitate data integrity checking.

Ibex testbench extended to generate the expected bits.

All other top-levels modified to add the new signals (which are mostly
ignored).

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
 2021-08-26 16:55:26 +01:00
Pirmin Vogel
14115ea3a8 [util] Document minimal requirement for Xilinx Vivado 
This is related to lowRISC/Ibex#1425.
 2021-08-26 14:42:26 +02:00
Greg Chadwick
3f9022a16d [rtl] Fix mtval for unaligned accesses 
Previously the raw incremented address was used which is the calculated
address + 4. This is confusing as it refers to a byte that wouldn't be
accessed (e.g. a lw at 0x8000009e which faults on the access to
0x8000000a0, would report an mtval of 0x8000000a2). With this change
mtval will refer to the first byte on the other half of the word
boundary the unaligned access crosses.
 2021-08-13 15:45:29 +01:00
Tom Roberts
65bf9c94f9 [rtl] Add LFSR permutation option 
Random constants are sent through the hierarchy as parameters in-line
with other OpenTitan modules.

Further detail on this mechanism can be found in lowrisc/opentitan#2229

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
 2021-08-10 16:13:02 +01:00
Greg Chadwick
dbc2b6f5dc [rtl/doc] Update ePMP CSR addresses and documentation 
mseccfg and mseccfgh have changed their addresses. This updates to the
newly allocated values.

The ePMP specification is now available as a versioned PDF,
documentation is updated to point to that removing the local PDF copy.
 2021-08-05 08:01:56 +01:00
Canberk Topal
9af580f6d9 [fpga] Add power analysis scripts to FPGA example 
This commit adds power analysis scripts to the Arty A7
example design. They can be used by setting the newly
added `FPGAPowerAnalysis` parameter to 1.

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
 2021-08-03 16:51:16 +01:00
Canberk Topal
1b1247e1de [fpga] Changed to 2p_ram for FPGA top level 
1-Port RAM is removed because of both execution and performance
issues. CLKIN1_PERIOD parameter is defined in clkgen module
for Vivado simulations.

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
 2021-08-03 16:51:16 +01:00
Canberk Topal
4b54d79fb4 [sw/fpga] coremark/link.ld update for FPGA sim 
This commit updates link.ld RAM length to include max BRAM capacity
for Arty A7-35. It also changes coremark makefile to include a .vmem
output, which then can be used for FPGA implementations.

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
 2021-08-03 16:51:16 +01:00
Tom Roberts
7c0b1ff160 [rtl] Add register slice on output of shadow core 
This decouples the shadow core from any timing paths and so should ease
implementation.

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
 2021-08-03 13:47:00 +01:00
Tom Roberts
4d729e20e5 [rtl] Buffer cleanup in top-level 
A minor change to use the Width parameter of prim_buf. No functional
impact but stops the hierarchy from being cluttered with hundreds of
generate contexts in the top level.

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
 2021-08-03 13:47:00 +01:00
Dawid Zimonczyk
d44966373e Added cast to enum 2021-07-26 09:48:41 +01:00
Tom Roberts
a1902004f9 [rtl] Add ResetAll parameter 
This parameter forces a reset of all registers inside the core. This is
required to guarantee a common starting point for lockstep and thus
prevent spurious lockstep failure alerts.

Another minor change in this commit rearranges the writeback stage
multiplexing to gate incoming lsu write data when not valid. This stops
any X values from the data bus propagating to the register file
signalling (and thus to the lockstep comparison) which would cause the
lockstep alert to be X. It has the side effect of possibly reducing
power consumption in the register file.

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
 2021-07-22 16:53:27 +01:00
Philipp Wagner
44777dc16d Copy verible-format configuration from OpenTitan 
This configuration is the closest we can get to our style guide right
now, so let's go with that.
 2021-07-22 13:17:21 +01:00
Philipp Wagner
d003d479ff Update lowrisc_ip to lowRISC/opentitan@da3ac7c4e 
Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
da3ac7c4eb23a92194874ad2daf2e5f9e3330572

* [memutil] Allow use without scrambled memories (Philipp Wagner)
* [prim_prince] Fix comment (Philipp Wagner)
* [memutil] Fix width mismatch (Philipp Wagner)
* [prim] Allow disabling SVAs ensuring REQ is held until ACK at run
  time (Pirmin Vogel)
* [prim] Fix typo that caused fifo_async to get stuck (Timothy Chen)
* [prim] Add a missing ROM_CFG_DEFAULT to prim_rom_pkg.sv (Rupert
  Swarbrick)
* [dvsim] Do not assume the build failed if "ERROR" is printed
  (Philipp Wagner)
* [prim_subreg_shadow] Invert meaning of SWACCESS in shadow/stage regs
  (Michael Schaffner)
* [prim_arb_tree/rv_plic_target] Remove TODOs due to a Vivado tool bug
  (Michael Schaffner)
* [primgen] Remove unused import (Philipp Wagner)
* [primgen] Add shebang (Philipp Wagner)
* [primgen] Make primgen "portable" again (Philipp Wagner)
* [dv] Small optimization in memutil (Philipp Wagner)
* [tools/ascent] updated ascent to use the --job-prefix option (Rasmus
  Madsen)
* [otp_ctrl] Remove invalid command error (Michael Schaffner)
* [tlul] Add some missing dependencies (Michael Schaffner)
* [otbn/otp_ctrl] Replicate dmem scrambling keystream (Michael
  Schaffner)
* [adc_ctrl] Various preparation steps for d2 (Timothy Chen)
* [tools/dvsim] Fix some VCS flags (Guillermo Maturana)
* Revert "[prim] Do remove prim_esc.core from the dependencies"
  (Rupert Swarbrick)
* [prim] Remove dependency of prim:esc on a hardware block (Rupert
  Swarbrick)
* [lint] prim_ram_1p_scr verilator lint fixes (Greg Chadwick)
* [dv] Add scrambled_ecc32_mem_area for memutils (Greg Chadwick)
* [dv] Add C++ memory scrambling model (Greg Chadwick)
* [tools/dsim] Fix non-LRM compliant code (Guillermo Maturana)
* [prim] Do remove prim_esc.core from the dependencies (Michael
  Schaffner)
* [dv/dv_utils] Improvement on `max` function (Cindy Chen)
* [alert_handler] Implement reverse ping feature (Michael Schaffner)
* [prim_esc] Split the prims into their own core file (Michael
  Schaffner)
* [dvsim] Fix GUI mode and launcher creation fixes (Srikrishna Iyer)
* [dv/common] Stress_all_with_rand_reset apply reset concurrently
  (Cindy Chen)
* [dv/all] update scoreboard `csr_addrs` accesses (Udi Jonnalagadda)
* [dv/csr_utils] update unmapped_addr calculation (Udi Jonnalagadda)
* [dv] Update intg alert names (Weicai Yang)
* [dv, flash_ctrl] Fix the intr test (Srikrishna Iyer)
* [prim_fifo_async] Fix a width calculation issue in case of Depth = 1
  (Michael Schaffner)
* [dv] Update VCS opt for uvm_hdl_* (Weicai Yang)
* [dv, util] Make poll_for_stop() opt-in (Srikrishna Iyer)
* [dvsim] Separate publish report option [PART1] (Cindy Chen)
* [dv/kmac/sram] reduce iterations of smoke test (Udi Jonnalagadda)
* [dv/stress_all_with_reset] Revert back IPs that uses apply_reset
  (Cindy Chen)
* [dv/edn_reset] Fix apply_reset to concurrently deassert resets
  (Cindy Chen)
* [dv] Update VCS cov merge opts (Srikrishna Iyer)
* [dv] Add TL integrity error test for CSR (Weicai Yang)
* [dv, chip] Remove USB clk driver (Srikrishna Iyer)
* [script/dvsim] Update output folder (Cindy Chen)
* [dv/edn_reset] Update IPs that overrides apply_reset task (Cindy
  Chen)
* [dv/edn_reset] Fix stress_all_with_rand_reset error (Cindy Chen)
* [dv/dv_base_scoreboard] remove duplicated code (Cindy Chen)
* [otbn,dv] Teach otbn_memutil to track expected end address (Rupert
  Swarbrick)
* [dv, dv_utils_pkg] Fix common int typedefs (Srikrishna Iyer)
* [prim_lfsr] Fix spyglass lint warnings (Michael Schaffner)
* [prim_clock_gating] Target 7series Xilinx devices (Philipp Wagner)
* [dv/edn_rst] Add coverage to collect edn reset and dut reset (Cindy
  Chen)
* [otp_ctrl/lc_ctrl] Add LC TAP register to control OTP test
  mechanisms (Michael Schaffner)
* [prim_alert*/prim_esc*] Rework placement of size_only bufs/flops
  (Michael Schaffner)
* [dv] fix a typo in tl_device_access_types_testplan (Weicai Yang)
* [prim_otp] Rework generic model to match new error behavior (Michael
  Schaffner)
* [dv/tlul_common_test] Add a testplan for TLUL integrity check (Cindy
  Chen)
* [dvsim] Allow recursive testplan import (Srikrishna Iyer)
* [primgen] Use verible-verilog-syntax for parsing (Mariusz Glebocki)
* [prim] Break always_comb block to avoid apparent loop (Rupert
  Swarbrick)
* [dvsim] Fix testplan bugs (Srikrishna Iyer)
* [fpv] update secded_gen (Cindy Chen)
* [dv/template] small fixes on index.md format (Cindy Chen)
* [prim_otp] Add a waiver for power signal unused in generic prim
  (Michael Schaffner)
* [simutil_verilator] Improve timeout handling (Rupert Swarbrick)
* [testplans] Rename entries with testpoints (Srikrishna Iyer)
* [dvsim/testplan] Fix the rendered testplan (Srikrishna Iyer)
* [dv/cov] exclude prim_lfsr and prim_prince (Udi Jonnalagadda)

Signed-off-by: Philipp Wagner <phw@lowrisc.org>
 2021-07-20 13:44:11 +01:00
Philipp Wagner
270cd91b38 Fix the verible-format CI job 
The toplevel core file got renamed, but the experimental verible-format
CI job wasn't updated in sync. Fix that.
 2021-07-15 15:47:57 +01:00
Philipp Wagner
ed46a5c9f5 [ci] Update dependencies to match OpenTitan 
Use the same dependencies as we use in OpenTitan to make it easier to
diagnose potential issues. No change in behavior expected.
 2021-07-14 11:12:09 +01:00
Tobias Wölfel
7032df0d8b [formal] Read Verilog files in Yosys 
All files read at this point should be Verilog and not SystemVerilog.
Do not use the SystemVerilog specifier for reading files.
 2021-07-14 11:02:46 +01:00
Tobias Wölfel
e1eaa1c804 [formal] Switch to new top level 
Use `ibex_top` instead of `ibex_core`.
 2021-07-14 11:02:46 +01:00