Commit graph

553 commits

Author SHA1 Message Date
Markus Wegmann
f21769f93a Rename example configs. 2017-01-02 12:23:45 +01:00
Markus Wegmann
ac23085ceb Fix wrong area report being read in case of multiple area reports 2017-01-02 11:20:52 +01:00
Markus Wegmann
6b1b60ffb0 Fix clock detection in ri5cly-manage.py 2017-01-02 04:06:23 +01:00
Markus Wegmann
e3e7ae0d9a Fix bug in ri5cly-manage.py where test_all did not get example configs 2017-01-02 03:13:27 +01:00
Markus Wegmann
c2abe72d67 Fix missing fetch reg assignment 2017-01-02 03:09:06 +01:00
Markus Wegmann
9ce07710e8 Fix missing register cycle 2017-01-02 02:53:53 +01:00
Markus Wegmann
289d874a2e Syntax fix 2017-01-02 02:47:43 +01:00
Markus Wegmann
4fb3b82c06 Fix syntax 2017-01-02 02:46:09 +01:00
Markus Wegmann
65503bae4b Try to patch prefetch buffer to not reaccess same instruction memory again if in stall 2017-01-02 02:40:42 +01:00
Markus Wegmann
886fd6c19d Change preamble of python script to run with python3 automatically 2017-01-02 01:44:58 +01:00
Markus Wegmann
e3717c6f48 Compile everything 2017-01-02 01:43:14 +01:00
Markus Wegmann
5ab7a9726e Add method to overwrite synopsys setup script 2017-01-02 00:52:16 +01:00
Markus Wegmann
40829665ef Report clock as well 2017-01-02 00:39:16 +01:00
Markus Wegmann
6141ffadd8 Minor fixes when no synthesized version found 2017-01-02 00:38:14 +01:00
Markus Wegmann
52ba034e5e Merge branch 'master' of iis-git.ee.ethz.ch:pulp-project/little-riscv 2017-01-02 00:30:58 +01:00
Markus Wegmann
87c4f51f2a Fix syntax in python script 2017-01-02 00:30:53 +01:00
Markus Wegmann
df1f583a38 Enforce Python3+ and change description 2017-01-02 00:29:52 +01:00
Markus Wegmann
b3b31e7faa Reorder options in ri5cly-manage.py 2017-01-02 00:27:58 +01:00
Markus Wegmann
5794d5a68d Add new testing capabilities to ri5cly-manage.py. Remove JUMP_IN_ID option from configs. 2017-01-02 00:23:14 +01:00
Markus Wegmann
415e970226 Better language in README concerning configuration 2016-12-31 18:51:48 +01:00
Markus Wegmann
809689a994 Update readme of littleRISCV 2016-12-31 18:46:52 +01:00
Markus Wegmann
793c996492 Readd dont-care extension of C instructions 2016-12-31 18:10:43 +01:00
Markus Wegmann
7a8123bddb Fix Offset 2016-12-31 17:48:12 +01:00
Markus Wegmann
13514e5462 Increment address after first fetch of overlapping instr word in prefetch buffer 2016-12-31 17:37:04 +01:00
Markus Wegmann
edb00022c9 Fix syntax 2016-12-31 17:30:22 +01:00
Markus Wegmann
bb3dbd7846 More fixes to compressed 2016-12-31 17:26:37 +01:00
Markus Wegmann
ab812ee384 Fix further 2016-12-31 16:57:46 +01:00
Markus Wegmann
503bb05f3e Fix misaligned detection 2016-12-31 16:39:25 +01:00
Markus Wegmann
c64fbf6bf3 Fix further 2016-12-31 16:33:49 +01:00
Markus Wegmann
3d2c4336ac Fix some bug 2016-12-31 16:22:15 +01:00
Markus Wegmann
042cc85010 Fix compressed instruction logic in small prefetch buffer
When we directly jump to an misaligned address with a C instruction, the
register cache is output, rather than the instruction memory output
2016-12-31 15:45:05 +01:00
Markus Wegmann
0be37479b1 Fix bug in prefetcher assigning wrong input to last_address register 2016-12-30 13:53:11 +01:00
Markus Wegmann
ad4603bc40 Fix folder overwrite bug 2016-12-30 00:45:49 +01:00
Markus Wegmann
346d14c5c8 Fix some issues and cleanup 2016-12-30 00:26:15 +01:00
Markus Wegmann
caa470303e Fix system call output 2016-12-30 00:00:02 +01:00
Markus Wegmann
334e22e47f Fix 2016-12-29 23:58:02 +01:00
Markus Wegmann
2b16f8e2a6 Add report functions 2016-12-29 23:55:43 +01:00
Markus Wegmann
6a6e2022b7 Add indication which file is overwriting the config 2016-12-29 23:27:21 +01:00
Markus Wegmann
7ff400071f Add message which config is being synthesized 2016-12-29 23:22:20 +01:00
Markus Wegmann
7f17101ff6 Fix 2016-12-29 23:18:49 +01:00
Markus Wegmann
26c1b81d63 Add new synthesize method and fix synthesize_all 2016-12-29 23:15:14 +01:00
Markus Wegmann
79ea1c2920 Fix bug bug concerning folder creation 2016-12-29 23:07:25 +01:00
Markus Wegmann
cdf7a20c56 Fix bug in ri5cly-manage.py 2016-12-29 23:04:09 +01:00
Markus Wegmann
edfa9c9b41 Add synthesizeAll method to ri5cly-manage.py 2016-12-29 22:59:44 +01:00
Markus Wegmann
fe071f4af9 Implement zipping of generated core 2016-12-29 22:26:42 +01:00
Markus Wegmann
d13f0ab003 Rename hardware loop config region. Add sample configurations to script folder 2016-12-29 22:16:27 +01:00
Markus Wegmann
0ffe4f9b4f Do some cleanup in the headers 2016-12-29 22:01:39 +01:00
Markus Wegmann
3fcb6b1c9f Rename export parameter in help of ri5cly-manage.py 2016-12-29 21:48:34 +01:00
Markus Wegmann
8b69782d90 Set execute rights on ri5cly-manage.py 2016-12-29 21:43:46 +01:00
Markus Wegmann
00a2c3a8fb Create a clean code generation script for littleRISCV called ri5cly-manage.py 2016-12-29 21:41:59 +01:00