Cairo Caplan 9df7ab1bab Modification of some Debug Modules parameters into (static) signals, as part of (#269) (#286) ... * [rtl] Changed the default number of performance counters from 0 to 10 (#214) * [rtl] Turning debug halt and exception addresses from parameters into signals (#269) * [doc] Updating the docs regarding the turning of debug halt and exception addresses into signals (#269) * Adding buildsim.log to .gitignore, as it is created by some make targets		2025-03-03 16:56:26 +01:00
..
cve2_alu.sv	Rename all modules to cve2 (#25)	2023-01-05 10:27:24 +01:00
cve2_branch_predict.sv	Rename all modules to cve2 (#25)	2023-01-05 10:27:24 +01:00
cve2_compressed_decoder.sv	Rename all modules to cve2 (#25)	2023-01-05 10:27:24 +01:00
cve2_controller.sv	removed unused irq_enable signal in controller (#178)	2023-12-12 13:40:59 +01:00
cve2_core.f	Rename all modules to cve2 (#25)	2023-01-05 10:27:24 +01:00
cve2_core.sv	Modification of some Debug Modules parameters into (static) signals, as part of (#269) (#286)	2025-03-03 16:56:26 +01:00
cve2_counter.sv	Rename all modules to cve2 (#25)	2023-01-05 10:27:24 +01:00
cve2_cs_registers.sv	RVFI CSRs improvements (#266)	2024-06-19 14:02:12 +02:00
cve2_csr.sv	Rename all modules to cve2 (#25)	2023-01-05 10:27:24 +01:00
cve2_decoder.sv	Feature/remove security (#52)	2023-02-28 14:03:42 +01:00
cve2_ex_block.sv	add fetch_enable_i (#118)	2023-06-01 14:41:31 +02:00
cve2_fetch_fifo.sv	fix design compiler (#270)	2024-05-27 15:23:26 +02:00
cve2_id_stage.sv	Do not count dret instruction when not in debug mode - it won't retire (#180)	2024-02-26 12:30:02 +01:00
cve2_if_stage.sv	Modification of some Debug Modules parameters into (static) signals, as part of (#269) (#286)	2025-03-03 16:56:26 +01:00
cve2_load_store_unit.sv	Feature/remove writeback stage (#56)	2023-05-31 14:44:59 +02:00
cve2_multdiv_fast.sv	Feature/remove writeback stage (#56)	2023-05-31 14:44:59 +02:00
cve2_multdiv_slow.sv	Feature/remove security (#52)	2023-02-28 14:03:42 +01:00
cve2_pkg.sv	add RVFI CSRs tracing (#184)	2024-02-26 13:05:23 +01:00
cve2_pmp.sv	Rename all modules to cve2 (#25)	2023-01-05 10:27:24 +01:00
cve2_pmp_reset_default.svh	Rename all modules to cve2 (#25)	2023-01-05 10:27:24 +01:00
cve2_prefetch_buffer.sv	remove branch predictor (#49)	2023-07-20 16:40:10 +02:00
cve2_register_file_ff.sv	fix verilator and add clk gating cell (#114)	2023-05-24 15:18:26 +02:00
cve2_top.sv	Modification of some Debug Modules parameters into (static) signals, as part of (#269) (#286)	2025-03-03 16:56:26 +01:00
cve2_top_tracing.sv	Modification of some Debug Modules parameters into (static) signals, as part of (#269) (#286)	2025-03-03 16:56:26 +01:00
cve2_tracer.sv	Rename all modules to cve2 (#25)	2023-01-05 10:27:24 +01:00
cve2_tracer_pkg.sv	Rename all modules to cve2 (#25)	2023-01-05 10:27:24 +01:00
cve2_wb.sv	add fetch_enable_i (#118)	2023-06-01 14:41:31 +02:00