The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

Sven Stucki bc51ae9305 Add sensible default in compressed decoder for one case		2015-09-01 12:58:49 +02:00
include	Simplified fetch logic a little bit	2015-09-01 09:53:03 +02:00
.gitignore	Added vim swap file	2015-07-24 15:26:32 +02:00
alu.sv	Readd ALU flag to EX stage, use it for branch decision	2015-08-31 13:06:43 +02:00
compressed_decoder.sv	Add sensible default in compressed decoder for one case	2015-09-01 12:58:49 +02:00
controller.sv	Debug support: Make single-stepping work again	2015-09-01 12:55:26 +02:00
cs_registers.sv	Fix linting errors/warnings and remove dead signals	2015-08-28 17:15:55 +02:00
debug_unit.sv	Rework pipeline flushes and exceptions	2015-08-31 10:02:55 +02:00
ex_stage.sv	Readd ALU flag to EX stage, use it for branch decision	2015-08-31 13:06:43 +02:00
exc_controller.sv	Readd ALU flag to EX stage, use it for branch decision	2015-08-31 13:06:43 +02:00
hwloop_controller.sv	Cosmetic changes in hwloop controller, ID and includes	2015-08-31 12:34:33 +02:00
hwloop_regs.sv	Fix hwloop code indentation	2015-08-31 12:33:27 +02:00
id_stage.sv	Simplified fetch logic a little bit	2015-09-01 09:53:03 +02:00
if_stage.sv	Simplified fetch logic a little bit	2015-09-01 09:53:03 +02:00
instr_core_interface.sv	Simplified fetch logic a little bit	2015-09-01 09:53:03 +02:00
load_store_unit.sv	Updated all file headers	2015-07-24 15:26:12 +02:00
mult.sv	Fix linting errors/warnings and remove dead signals	2015-08-28 17:15:55 +02:00
register_file.sv	Fix linting errors/warnings and remove dead signals	2015-08-28 17:15:55 +02:00
riscv_core.sv	Remove TCDM_ADDR_PRECAL and some other cleanup	2015-08-31 12:35:26 +02:00