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Updated fpga wally wrapper to work with the ILA.

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This commit is contained in:
Ross Thompson 2023-06-19 12:15:48 -05:00
parent f5cee3fb66
commit 1a23f1360f
2 changed files with 2 additions and 3 deletions
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3
fpga/generator/wally.tcl
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@ -83,8 +83,7 @@ if {$board=="ArtyA7"} {
source ../constraints/small-debug.xdc
} else {
# *** RT: 16 June 2023 must add back in the debugger
#source ../constraints/debug4.xdc
source ../constraints/debug4.xdc
}

2
fpga/src/wallypipelinedsocwrapper.sv
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@ -64,7 +64,7 @@ module wallypipelinedsocwrapper (
);
`include "parameter-defs.vh"
wallypipelinedsoc #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
wallypipelinedsoc #(P) wallypipelinedsoc(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
.HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
.HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
.UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK);