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Merge branch 'main' of https://github.com/openhwgroup/cvw

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This commit is contained in:
Ross Thompson 2023-06-18 16:37:19 -05:00
commit f5cee3fb66
12 changed files with 55 additions and 40 deletions
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8
benchmarks/embench/Makefile
View file

@ -16,10 +16,18 @@ buildsize: build_speedopt_size build_sizeopt_size
# uses the build_all.py python file to build the tests in addins/embench-iot/bd_speed/ optimized for speed and size
build_speedopt_speed:
$(embench_dir)/build_all.py --builddir=bd_speedopt_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S" --cflags="-O2 -nostartfiles"
# remove files not used in embench1.0 When changing to 2.0, restore these files
#rm -rf $(embench_dir)/bd_speedopt_speed/src/md5sum
#rm -rf $(embench_dir)/bd_speedopt_speed/src/tarfind
#rm -rf $(embench_dir)/bd_speedopt_speed/src/primecount
find $(embench_dir)/bd_speedopt_speed/ -type f ! -name "*.*" | while read f; do cp "$$f" "$$f.elf"; done
build_sizeopt_speed:
$(embench_dir)/build_all.py --builddir=bd_sizeopt_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S" --cflags="-Os -nostartfiles"
# remove files not used in embench1.0 When changing to 2.0, restore these files
#rm -rf $(embench_dir)/bd_sizeopt_speed/src/md5sum
#rm -rf $(embench_dir)/bd_sizeopt_speed/src/tarfind
#rm -rf $(embench_dir)/bd_sizeopt_speed/src/primecount
find $(embench_dir)/bd_sizeopt_speed/ -type f ! -name "*.*" | while read f; do cp "$$f" "$$f.elf"; done
# uses the build_all.py python file to build the tests in addins/embench-iot/bd_speed/ optimized for speed and size

4
sim/imperas.ic
View file

@ -1,7 +1,7 @@
#--mpdconsole
#--gdbconsole
--showoverrides
--showcommands
#--showoverrides
#--showcommands
# Core settings
--override cpu/priv_version=1.12

14
sim/wally-imperas-cov.do
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@ -29,19 +29,19 @@ vlog +incdir+../config/$1 \
+define+USE_IMPERAS_DV \
+incdir+$env(IMPERAS_HOME)/ImpPublic/include/host \
+incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host \
$env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-api-pkg.sv \
$env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-trace.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/rvvi-pkg.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/imperasDV-api-pkg.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2api.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2log.sv \
$env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviApiPkg.sv \
$env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviTrace.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvPkg.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvApiPkg.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2api.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2log.sv \
\
+define+INCLUDE_TRACE2COV +define+COVER_BASE_RV64I +define+COVER_LEVEL_DV_PR_EXT \
+define+COVER_RV64I \
+define+COVER_RV64C \
+define+COVER_RV64M \
+incdir+$env(IMPERAS_HOME)/ImpProprietary/source/host/riscvISACOV/source \
$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2cov.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv \
\
../src/cvw.sv \
../testbench/testbench_imperas.sv \

2
sim/wally-imperas-no-idv.do
View file

@ -26,7 +26,7 @@ vlib work
# *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN. For now just live with the warnings.
vlog +incdir+../config/$1 \
+incdir+../config/shared \
../../external/ImperasDV-HMC/Imperas/ImpPublic/source/host/rvvi/rvvi-trace.sv \
../../external/ImperasDV-HMC/Imperas/ImpPublic/source/host/rvvi/rvviTrace.sv \
../src/cvw.sv \
../testbench/testbench_imperas.sv \
../testbench/common/*.sv \

14
sim/wally-imperas.do
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@ -30,13 +30,13 @@ vlog +incdir+../config/$1 \
+define+USE_IMPERAS_DV \
+incdir+$env(IMPERAS_HOME)/ImpPublic/include/host \
+incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host \
$env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-api-pkg.sv \
$env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-trace.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/rvvi-pkg.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/imperasDV-api-pkg.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2api.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2log.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2cov.sv \
$env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviApiPkg.sv \
$env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviTrace.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvPkg.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvApiPkg.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2api.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2log.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv \
../src/cvw.sv \
../testbench/testbench_imperas.sv \
../testbench/common/*.sv \

14
sim/wally-linux-imperas.do
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@ -53,13 +53,13 @@ if {$2 eq "buildroot" || $2 eq "buildroot-checkpoint"} {
+incdir+../config/shared \
+incdir+$env(IMPERAS_HOME)/ImpPublic/include/host \
+incdir+$env(IMPERAS_HOME)/ImpProprietary/include/host \
$env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-api-pkg.sv \
$env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvvi-trace.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/rvvi-pkg.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/imperasDV-api-pkg.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2api.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2log.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2cov.sv \
$env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviApiPkg.sv \
$env(IMPERAS_HOME)/ImpPublic/source/host/rvvi/rvviTrace.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvPkg.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/idvApiPkg.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2api.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2log.sv \
$env(IMPERAS_HOME)/ImpProprietary/source/host/idv/trace2cov.sv \
../src/cvw.sv \
../testbench/testbench-linux-imperas.sv \
../testbench/common/*.sv ../src/*/*.sv \

3
src/ieu/controller.sv
View file

@ -339,5 +339,6 @@ module controller import cvw::*; #(parameter cvw_t P) (
// the synchronous DTIM cannot read immediately after write
// a cache cannot read or write immediately after a write
assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & P.DCACHE_SUPPORTED)) | (|AtomicD));
// atomic operations are also detected as MemRWD[1]
assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & P.DCACHE_SUPPORTED)));
endmodule

2
testbench/common/riscvassertions.sv
View file

@ -56,6 +56,8 @@ module riscvassertions import cvw::*; #(parameter cvw_t P);
assert (P.IDIV_ON_FPU == 0 || P.F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED");
assert (P.SSTC_SUPPORTED == 0 || (P.S_SUPPORTED)) else $error("SSTC requires S_SUPPORTED");
assert ((P.ZMMUL_SUPPORTED == 0) || (P.M_SUPPORTED ==0)) else $error("At most one of ZMMUL_SUPPORTED and M_SUPPORTED can be enabled");
assert ((P.ZICNTR_SUPPORTED == 0) || (P.ZICSR_SUPPORTED == 1)) else $error("ZICNTR_SUPPORTED requires ZICSR_SUPPORTED");
assert ((P.ZIHPM_SUPPORTED == 0) || (P.ZICNTR_SUPPORTED == 1)) else $error("ZIPHM_SUPPORTED requires ZICNTR_SUPPORTED");
end
endmodule

6
testbench/testbench-linux-imperas.sv
View file

@ -30,7 +30,7 @@
// `define USE_IMPERAS_DV
`ifdef USE_IMPERAS_DV
`include "rvvi/imperasDV.svh"
`include "idv/idv.svh"
`endif
`define DEBUG_TRACE 0
@ -55,7 +55,7 @@ module testbench;
`ifdef USE_IMPERAS_DV
import rvviPkg::*;
import idvPkg::*;
import rvviApiPkg::*;
import idvApiPkg::*;
`endif
@ -302,7 +302,7 @@ module testbench;
initial begin
int iter;
#1;
MAX_ERRS = 3;
IDV_MAX_ERRS = 3;
// Initialize REF (do this before initializing the DUT)
if (!rvviVersionCheck(RVVI_API_VERSION)) begin

6
testbench/testbench_imperas.sv
View file

@ -32,7 +32,7 @@
// `define USE_IMPERAS_DV
`ifdef USE_IMPERAS_DV
`include "rvvi/imperasDV.svh"
`include "idv/idv.svh"
`endif
import cvw::*;
@ -41,7 +41,7 @@ module testbench;
parameter DEBUG=0;
`ifdef USE_IMPERAS_DV
import rvviPkg::*;
import idvPkg::*;
import rvviApiPkg::*;
import idvApiPkg::*;
`endif
@ -145,7 +145,7 @@ module testbench;
initial begin
MAX_ERRS = 3;
IDV_MAX_ERRS = 3;
// Initialize REF (do this before initializing the DUT)
if (!rvviVersionCheck(RVVI_API_VERSION)) begin

18
testbench/tests.vh
View file

@ -75,26 +75,26 @@ string tvpaths[] = '{
string embench[] = '{
`EMBENCH,
"bd_speedopt_speed/src/nsichneu/nsichneu",
"bd_speedopt_speed/src/cubic/cubic", // cubic is likely going to removed when embench 2.0 launches
"bd_speedopt_speed/src/aha-mont64/aha-mont64",
"bd_speedopt_speed/src/crc32/crc32",
"bd_speedopt_speed/src/cubic/cubic", // cubic is likely going to removed when embench 2.0 launches
"bd_speedopt_speed/src/edn/edn",
"bd_speedopt_speed/src/huffbench/huffbench",
"bd_speedopt_speed/src/matmult-int/matmult-int",
// "bd_speedopt_speed/src/md5sum/md5sum", //commenting out tests from embench 2.0. When embench 2.0 launches stabilty, add these tests back
"bd_speedopt_speed/src/md5sum/md5sum", //commenting out tests from embench 2.0. When embench 2.0 launches stabilty, add these tests back
"bd_speedopt_speed/src/minver/minver",
"bd_speedopt_speed/src/nettle-aes/nettle-aes",
"bd_speedopt_speed/src/nettle-sha256/nettle-sha256",
"bd_speedopt_speed/src/nsichneu/nsichneu",
"bd_speedopt_speed/src/nbody/nbody",
"bd_speedopt_speed/src/picojpeg/picojpeg",
// "bd_speedopt_speed/src/primecount/primecount",
"bd_speedopt_speed/src/primecount/primecount",
"bd_speedopt_speed/src/qrduino/qrduino",
"bd_speedopt_speed/src/sglib-combined/sglib-combined",
"bd_speedopt_speed/src/slre/slre",
"bd_speedopt_speed/src/st/st",
"bd_speedopt_speed/src/statemate/statemate",
// "bd_speedopt_speed/src/tarfind/tarfind",
"bd_speedopt_speed/src/tarfind/tarfind",
"bd_speedopt_speed/src/ud/ud",
"bd_speedopt_speed/src/wikisort/wikisort",
"bd_sizeopt_speed/src/aha-mont64/aha-mont64",
@ -103,20 +103,20 @@ string tvpaths[] = '{
"bd_sizeopt_speed/src/edn/edn",
"bd_sizeopt_speed/src/huffbench/huffbench",
"bd_sizeopt_speed/src/matmult-int/matmult-int",
// "bd_sizeopt_speed/src/md5sum/md5sum",
"bd_sizeopt_speed/src/md5sum/md5sum",
"bd_sizeopt_speed/src/minver/minver",
"bd_sizeopt_speed/src/nbody/nbody",
"bd_sizeopt_speed/src/nettle-aes/nettle-aes",
"bd_sizeopt_speed/src/nettle-sha256/nettle-sha256",
"bd_sizeopt_speed/src/nsichneu/nsichneu",
"bd_sizeopt_speed/src/picojpeg/picojpeg",
// "bd_sizeopt_speed/src/primecount/primecount",
"bd_sizeopt_speed/src/primecount/primecount",
"bd_sizeopt_speed/src/qrduino/qrduino",
"bd_sizeopt_speed/src/sglib-combined/sglib-combined",
"bd_sizeopt_speed/src/slre/slre",
"bd_sizeopt_speed/src/st/st",
"bd_sizeopt_speed/src/statemate/statemate",
// "bd_sizeopt_speed/src/tarfind/tarfind",
"bd_sizeopt_speed/src/tarfind/tarfind",
"bd_sizeopt_speed/src/ud/ud",
"bd_sizeopt_speed/src/wikisort/wikisort"
};
@ -1466,7 +1466,7 @@ string arch64zbb[] = '{
"rv64i_m/B/src/andn-01.S",
"rv64i_m/B/src/orn-01.S",
"rv64i_m/B/src/xnor-01.S",
"rv64i_m/B/src/zext.h-01.S",
"rv64i_m/B/src/zext.h_64-01.S",
"rv64i_m/B/src/sext.b-01.S",
"rv64i_m/B/src/sext.h-01.S",
"rv64i_m/B/src/clz-01.S",

4
tests/coverage/fpu.S
View file

@ -156,6 +156,10 @@ main:
.word 0x43007053 // illegal fcvt.d.* (bad Rs2D)
.word 0x42207053 // illegal fcvt.d.* (bad Rs2D[1])
# Test floating point convert to integer and using result
fcvt.w.s t0, f0
add t1, t0, t0
j done
.section .data