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Increased genesys 2 clock speed to 40MHz!

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This commit is contained in:
Rose Thompson 2025-05-30 13:06:26 -07:00
parent 23c0c751da
commit 56826c9e51
2 changed files with 6 additions and 6 deletions
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4
fpga/generator/Makefile
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@ -28,8 +28,8 @@ vcu108: FPGA_VCU
genesys2: export XILINX_PART := xc7k325tffg900-2
genesys2: export XILINX_BOARD := digilentinc.com:genesys2:part0:1.1
genesys2: export board := genesys2
genesys2: export SYSTEMCLOCK := 25000000
genesys2: export MAXSDCCLOCK := 12500000
genesys2: export SYSTEMCLOCK := 40000000
genesys2: export MAXSDCCLOCK := 10000000
genesys2: FPGA_GENESYS2
# variables computed from config