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Increased genesys 2 clock speed to 40MHz!

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This commit is contained in:
Rose Thompson 2025-05-30 13:06:26 -07:00
parent 23c0c751da
commit 56826c9e51
2 changed files with 6 additions and 6 deletions
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4
fpga/generator/Makefile
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@ -28,8 +28,8 @@ vcu108: FPGA_VCU
genesys2: export XILINX_PART := xc7k325tffg900-2 genesys2: export XILINX_PART := xc7k325tffg900-2
genesys2: export XILINX_BOARD := digilentinc.com:genesys2:part0:1.1 genesys2: export XILINX_BOARD := digilentinc.com:genesys2:part0:1.1
genesys2: export board := genesys2 genesys2: export board := genesys2
genesys2: export SYSTEMCLOCK := 25000000 genesys2: export SYSTEMCLOCK := 40000000
genesys2: export MAXSDCCLOCK := 12500000 genesys2: export MAXSDCCLOCK := 10000000
genesys2: FPGA_GENESYS2 genesys2: FPGA_GENESYS2
# variables computed from config # variables computed from config

8
linux/devicetree/wally-genesys2.dts
View file

@ -21,8 +21,8 @@
cpus { cpus {
#address-cells = <0x01>; #address-cells = <0x01>;
#size-cells = <0x00>; #size-cells = <0x00>;
clock-frequency = <25000000>; clock-frequency = <40000000>;
timebase-frequency = <25000000>; timebase-frequency = <40000000>;
cpu@0 { cpu@0 {
phandle = <0x01>; phandle = <0x01>;
@ -54,7 +54,7 @@
refclk: refclk { refclk: refclk {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "fixed-clock"; compatible = "fixed-clock";
clock-frequency = <25000000>; clock-frequency = <40000000>;
clock-output-names = "xtal"; clock-output-names = "xtal";
}; };
@ -73,7 +73,7 @@
uart@10000000 { uart@10000000 {
interrupts = <0x0a>; interrupts = <0x0a>;
interrupt-parent = <0x03>; interrupt-parent = <0x03>;
clock-frequency = <25000000>; clock-frequency = <40000000>;
reg = <0x00 0x10000000 0x00 0x100>; reg = <0x00 0x10000000 0x00 0x100>;
compatible = "ns16550a"; compatible = "ns16550a";
}; };