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Turned off RVVI by default.

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This commit is contained in:
Jacob Pease 2024-08-08 13:50:11 -05:00
parent 9976f6087e
commit ed0c826d74
1 changed files with 1 additions and 1 deletions
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2
fpga/src/fpgaTopArtyA7.sv
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@ -28,7 +28,7 @@
import cvw::*;
module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 1)
module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
(input default_100mhz_clk,
(* mark_debug = "true" *) input resetn,
input south_reset,