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https://github.com/openhwgroup/cvw.git
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Merge pull request #577 from davidharrishmc/dev
Zfh fix and typo corrections
This commit is contained in:
Rose Thompson
GitHub
commit
ed0f0d924b
22 changed files with 396 additions and 201 deletions
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@ -41,6 +41,7 @@ localparam ZICNTR_SUPPORTED = 1;
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localparam ZIHPM_SUPPORTED = 1;
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localparam COUNTERS = 12'd32;
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localparam ZFH_SUPPORTED = 0;
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localparam ZFA_SUPPORTED = 0;
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localparam SSTC_SUPPORTED = 1;
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localparam ZICBOM_SUPPORTED = 1;
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localparam ZICBOZ_SUPPORTED = 1;
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@ -41,6 +41,7 @@ localparam COUNTERS = 12'd0;
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localparam ZICNTR_SUPPORTED = 0;
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localparam ZIHPM_SUPPORTED = 0;
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localparam ZFH_SUPPORTED = 0;
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localparam ZFA_SUPPORTED = 0;
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localparam SSTC_SUPPORTED = 0;
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localparam ZICBOM_SUPPORTED = 0;
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localparam ZICBOZ_SUPPORTED = 0;
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@ -42,6 +42,7 @@ localparam COUNTERS = 12'd32;
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localparam ZICNTR_SUPPORTED = 1;
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localparam ZIHPM_SUPPORTED = 1;
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localparam ZFH_SUPPORTED = 0;
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localparam ZFA_SUPPORTED = 0;
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localparam SSTC_SUPPORTED = 1;
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localparam ZICBOM_SUPPORTED = 1;
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localparam ZICBOZ_SUPPORTED = 1;
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@ -41,6 +41,7 @@ localparam COUNTERS = 0;
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localparam ZICNTR_SUPPORTED = 0;
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localparam ZIHPM_SUPPORTED = 0;
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localparam ZFH_SUPPORTED = 0;
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localparam ZFA_SUPPORTED = 0;
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localparam SSTC_SUPPORTED = 0;
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localparam ZICBOM_SUPPORTED = 0;
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localparam ZICBOZ_SUPPORTED = 0;
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@ -40,6 +40,7 @@ localparam COUNTERS = 12'd32;
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localparam ZICNTR_SUPPORTED = 1;
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localparam ZIHPM_SUPPORTED = 1;
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localparam ZFH_SUPPORTED = 0;
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localparam ZFA_SUPPORTED = 0;
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localparam SSTC_SUPPORTED = 0;
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localparam ZICBOM_SUPPORTED = 0;
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localparam ZICBOZ_SUPPORTED = 0;
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@ -31,7 +31,7 @@
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localparam XLEN = 32'd64;
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// IEEE 754 compliance
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localparam IEEE754 = 0;
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localparam IEEE754 = 1;
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// MISA RISC-V configuration per specification
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localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 );
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@ -41,6 +41,7 @@ localparam COUNTERS = 12'd32;
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localparam ZICNTR_SUPPORTED = 1;
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localparam ZIHPM_SUPPORTED = 1;
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localparam ZFH_SUPPORTED = 1;
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localparam ZFA_SUPPORTED = 0;
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localparam SSTC_SUPPORTED = 0;
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localparam ZICBOM_SUPPORTED = 0;
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localparam ZICBOZ_SUPPORTED = 0;
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@ -40,7 +40,8 @@ localparam ZIFENCEI_SUPPORTED = 1;
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localparam COUNTERS = 12'd32;
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localparam ZICNTR_SUPPORTED = 1;
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localparam ZIHPM_SUPPORTED = 1;
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localparam ZFH_SUPPORTED = 0;
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localparam ZFH_SUPPORTED = 1;
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localparam ZFA_SUPPORTED = 0;
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localparam SSTC_SUPPORTED = 1;
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localparam ZICBOM_SUPPORTED = 1;
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localparam ZICBOZ_SUPPORTED = 1;
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@ -41,6 +41,7 @@ localparam COUNTERS = 0;
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localparam ZICNTR_SUPPORTED = 0;
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localparam ZIHPM_SUPPORTED = 0;
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localparam ZFH_SUPPORTED = 0;
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localparam ZFA_SUPPORTED = 0;
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localparam SSTC_SUPPORTED = 0;
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localparam ZICBOM_SUPPORTED = 0;
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localparam ZICBOZ_SUPPORTED = 0;
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@ -65,33 +65,29 @@ localparam H_NF = 32'd10;
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localparam H_BIAS = 32'd15;
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localparam H_FMT = 2'd2;
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// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits
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localparam FLEN = (Q_SUPPORTED ? Q_LEN : D_SUPPORTED ? D_LEN : S_LEN);
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localparam NE = (Q_SUPPORTED ? Q_NE : D_SUPPORTED ? D_NE : S_NE);
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localparam NF = (Q_SUPPORTED ? Q_NF : D_SUPPORTED ? D_NF : S_NF);
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localparam FMT = (Q_SUPPORTED ? 2'd3 : D_SUPPORTED ? 2'd1 : 2'd0);
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localparam BIAS = (Q_SUPPORTED ? Q_BIAS : D_SUPPORTED ? D_BIAS : S_BIAS);
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/* Delete once tested dh 10/10/22
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localparam FLEN = (Q_SUPPORTED ? Q_LEN : D_SUPPORTED ? D_LEN : F_SUPPORTED ? S_LEN : H_LEN);
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localparam NE = (Q_SUPPORTED ? Q_NE : D_SUPPORTED ? D_NE : F_SUPPORTED ? S_NE : H_NE);
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localparam NF = (Q_SUPPORTED ? Q_NF : D_SUPPORTED ? D_NF : F_SUPPORTED ? S_NF : H_NF);
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localparam FMT = (Q_SUPPORTED ? 2'd3 : D_SUPPORTED ? 2'd1 : F_SUPPORTED ? 2'd0 : 2'd2);
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localparam BIAS = (Q_SUPPORTED ? Q_BIAS : D_SUPPORTED ? D_BIAS : F_SUPPORTED ? S_BIAS : H_BIAS);*/
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// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits (for longest format supported)
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localparam FLEN = Q_SUPPORTED ? Q_LEN : D_SUPPORTED ? D_LEN : S_LEN;
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localparam NE = Q_SUPPORTED ? Q_NE : D_SUPPORTED ? D_NE : S_NE;
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localparam NF = Q_SUPPORTED ? Q_NF : D_SUPPORTED ? D_NF : S_NF;
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localparam FMT = Q_SUPPORTED ? 2'd3 : D_SUPPORTED ? 2'd1 : 2'd0;
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localparam BIAS = Q_SUPPORTED ? Q_BIAS : D_SUPPORTED ? D_BIAS : S_BIAS;
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// Floating point constants needed for FPU paramerterization
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localparam FPSIZES = ((32)'(Q_SUPPORTED)+(32)'(D_SUPPORTED)+(32)'(F_SUPPORTED)+(32)'(ZFH_SUPPORTED));
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localparam FMTBITS = ((32)'(FPSIZES>=3)+1);
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localparam LEN1 = ((D_SUPPORTED & (FLEN != D_LEN)) ? D_LEN : (F_SUPPORTED & (FLEN != S_LEN)) ? S_LEN : H_LEN);
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localparam NE1 = ((D_SUPPORTED & (FLEN != D_LEN)) ? D_NE : (F_SUPPORTED & (FLEN != S_LEN)) ? S_NE : H_NE);
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localparam NF1 = ((D_SUPPORTED & (FLEN != D_LEN)) ? D_NF : (F_SUPPORTED & (FLEN != S_LEN)) ? S_NF : H_NF);
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localparam FMT1 = ((D_SUPPORTED & (FLEN != D_LEN)) ? 2'd1 : (F_SUPPORTED & (FLEN != S_LEN)) ? 2'd0 : 2'd2);
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localparam BIAS1 = ((D_SUPPORTED & (FLEN != D_LEN)) ? D_BIAS : (F_SUPPORTED & (FLEN != S_LEN)) ? S_BIAS : H_BIAS);
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localparam LEN2 = ((F_SUPPORTED & (LEN1 != S_LEN)) ? S_LEN : H_LEN);
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localparam NE2 = ((F_SUPPORTED & (LEN1 != S_LEN)) ? S_NE : H_NE);
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localparam NF2 = ((F_SUPPORTED & (LEN1 != S_LEN)) ? S_NF : H_NF);
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localparam FMT2 = ((F_SUPPORTED & (LEN1 != S_LEN)) ? 2'd0 : 2'd2);
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localparam BIAS2 = ((F_SUPPORTED & (LEN1 != S_LEN)) ? S_BIAS : H_BIAS);
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// LEN1/NE1/NF1/FNT1 is the size of the second longest supported format
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localparam FPSIZES = (32)'(Q_SUPPORTED)+(32)'(D_SUPPORTED)+(32)'(F_SUPPORTED)+(32)'(ZFH_SUPPORTED);
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localparam FMTBITS = (32)'(FPSIZES>=3)+1;
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localparam LEN1 = (FLEN > D_LEN) ? D_LEN : (FLEN > S_LEN) ? S_LEN : H_LEN;
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localparam NE1 = (FLEN > D_LEN) ? D_NE : (FLEN > S_LEN) ? S_NE : H_NE;
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localparam NF1 = (FLEN > D_LEN) ? D_NF : (FLEN > S_LEN) ? S_NF : H_NF;
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localparam FMT1 = (FLEN > D_LEN) ? 2'd1 : (FLEN > S_LEN) ? 2'd0 : 2'd2;
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localparam BIAS1 = (FLEN > D_LEN) ? D_BIAS : (FLEN > S_LEN) ? S_BIAS : H_BIAS;
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// LEN2 etc is the size of the third longest supported format
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localparam LEN2 = (LEN1 > S_LEN) ? S_LEN : H_LEN;
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localparam NE2 = (LEN1 > S_LEN) ? S_NE : H_NE;
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localparam NF2 = (LEN1 > S_LEN) ? S_NF : H_NF;
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localparam FMT2 = (LEN1 > S_LEN) ? 2'd0 : 2'd2;
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localparam BIAS2 = (LEN1 > S_LEN) ? S_BIAS : H_BIAS;
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// divider r and rk (bits per digit, bits per cycle)
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localparam LOGR = $clog2(RADIX); // r = log(R) bits per digit
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@ -14,6 +14,7 @@ localparam cvw_t P = '{
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ZICNTR_SUPPORTED : ZICNTR_SUPPORTED,
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ZIHPM_SUPPORTED : ZIHPM_SUPPORTED,
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ZFH_SUPPORTED : ZFH_SUPPORTED,
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ZFA_SUPPORTED : ZFA_SUPPORTED,
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SSTC_SUPPORTED : SSTC_SUPPORTED,
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VIRTMEM_SUPPORTED : VIRTMEM_SUPPORTED,
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VECTORED_INTERRUPTS_SUPPORTED : VECTORED_INTERRUPTS_SUPPORTED,
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@ -49,6 +49,7 @@ typedef struct packed {
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logic ZICNTR_SUPPORTED;
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logic ZIHPM_SUPPORTED;
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logic ZFH_SUPPORTED;
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logic ZFA_SUPPORTED;
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logic SSTC_SUPPORTED;
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logic VIRTMEM_SUPPORTED;
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logic VECTORED_INTERRUPTS_SUPPORTED;
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@ -38,7 +38,7 @@ module fctrl import cvw::*; #(parameter cvw_t P) (
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input logic FDivBusyE, // is the divider busy
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// instruction
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input logic [31:0] InstrD, // the full instruction
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input logic [6:0] Funct7D, // bits 31:25 of instruction - may contain percision
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input logic [6:0] Funct7D, // bits 31:25 of instruction - may contain precision
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input logic [6:0] OpD, // bits 6:0 of instruction
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input logic [4:0] Rs2D, // bits 24:20 of instruction
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input logic [2:0] Funct3D, // bits 14:12 of instruction - may contain rounding mode
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@ -84,8 +84,9 @@ module fctrl import cvw::*; #(parameter cvw_t P) (
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assign Fmt = Funct7D[1:0];
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assign Fmt2 = Rs2D[1:0]; // source format for fcvt fp->fp
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assign SupportedFmt = (Fmt == 2'b00 | (Fmt == 2'b01 & P.D_SUPPORTED) |
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(Fmt == 2'b10 & P.ZFH_SUPPORTED) | (Fmt == 2'b11 & P.Q_SUPPORTED));
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assign SupportedFmt = (Fmt == 2'b00 | (Fmt == 2'b01 & P.D_SUPPORTED) |
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(Fmt == 2'b10 & P.ZFH_SUPPORTED & {OpD[6:4], OpD[1:0]} != 5'b10011) | // fma not supported for Zfh
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(Fmt == 2'b11 & P.Q_SUPPORTED));
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assign SupportedFmt2 = (Fmt2 == 2'b00 | (Fmt2 == 2'b01 & P.D_SUPPORTED) |
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(Fmt2 == 2'b10 & P.ZFH_SUPPORTED) | (Fmt2 == 2'b11 & P.Q_SUPPORTED));
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@ -69,9 +69,9 @@ module fcvt import cvw::*; #(parameter cvw_t P) (
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assign Int64 = OpCtrl[1];
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assign IntToFp = OpCtrl[2];
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// choose the ouptut format depending on the opperation
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// - fp -> fp: OpCtrl contains the percision of the output
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// - int -> fp: Fmt contains the percision of the output
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// choose the output format depending on the opperation
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// - fp -> fp: OpCtrl contains the precision of the output
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// - int -> fp: Fmt contains the precision of the output
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if (P.FPSIZES == 2)
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assign OutFmt = IntToFp ? Fmt : (OpCtrl[1:0] == P.FMT);
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else if (P.FPSIZES == 3 | P.FPSIZES == 4)
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@ -263,35 +263,38 @@ module fpu import cvw::*; #(parameter cvw_t P) (
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.ToInt(FWriteIntE), .XZero(XZeroE), .Fmt(FmtE), .Ce(CeE), .ShiftAmt(CvtShiftAmtE),
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.ResSubnormUf(CvtResSubnormUfE), .Cs(CsE), .IntZero(IntZeroE), .LzcIn(CvtLzcInE));
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// NaN Box SrcA to convert integer to requested FP size
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// NaN Box SrcA to convert integer to requested FP size for fmv.*.x
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if(P.FPSIZES == 1) assign AlignedSrcAE = {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE};
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else if(P.FPSIZES == 2)
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mux2 #(P.FLEN) SrcAMux ({{P.FLEN-P.LEN1{1'b1}}, ForwardedSrcAE[P.LEN1-1:0]}, {{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE}, FmtE, AlignedSrcAE);
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else if(P.FPSIZES == 3 | P.FPSIZES == 4)
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mux4 #(P.FLEN) SrcAMux ({{P.FLEN-P.S_LEN{1'b1}}, ForwardedSrcAE[P.S_LEN-1:0]},
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{{P.FLEN-P.D_LEN{1'b1}}, ForwardedSrcAE[P.D_LEN-1:0]},
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else if(P.FPSIZES == 3 | P.FPSIZES == 4) begin
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localparam XD_LEN = P.D_LEN < P.XLEN ? P.D_LEN : P.XLEN; // shorter of D_LEN and XLEN
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mux3 #(P.FLEN) SrcAMux ({{P.FLEN-P.S_LEN{1'b1}}, ForwardedSrcAE[P.S_LEN-1:0]},
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{{P.FLEN-XD_LEN{1'b1}}, ForwardedSrcAE[XD_LEN-1:0]},
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{{P.FLEN-P.H_LEN{1'b1}}, ForwardedSrcAE[P.H_LEN-1:0]},
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{{P.FLEN-P.XLEN{1'b1}}, ForwardedSrcAE}, FmtE, AlignedSrcAE); // NaN boxing zeroes
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FmtE, AlignedSrcAE); // NaN boxing zeroes
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end
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// select a result that may be written to the FP register
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mux3 #(P.FLEN) FResMux(SgnResE, AlignedSrcAE, CmpFpResE, {OpCtrlE[2], &OpCtrlE[1:0]}, PreFpResE);
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assign PreNVE = CmpNVE&(OpCtrlE[2]|FWriteIntE);
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// select the result that may be written to the integer register with fmv - to IEU
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// select the result that may be written to the integer register with fmv.x.*
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if(P.FPSIZES == 1) begin
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assign mvsgn = XE[P.FLEN-1];
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assign SgnExtXE = XE;
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end else if(P.FPSIZES == 2) begin
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mux2 #(1) sgnmux (XE[P.LEN1-1], XE[P.FLEN-1],FmtE, mvsgn);
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mux2 #(1) sgnmux (XE[P.LEN1-1], XE[P.FLEN-1],FmtE, mvsgn);
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mux2 #(P.FLEN) sgnextmux ({{P.FLEN-P.LEN1{mvsgn}}, XE[P.LEN1-1:0]}, XE, FmtE, SgnExtXE);
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end else if(P.FPSIZES == 3 | P.FPSIZES == 4) begin
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mux4 #(1) sgnmux (XE[P.H_LEN-1], XE[P.S_LEN-1], XE[P.D_LEN-1], XE[P.LLEN-1], FmtE, mvsgn);
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mux4 #(P.FLEN) fmulzeromux ({{P.FLEN-P.H_LEN{mvsgn}}, XE[P.H_LEN-1:0]},
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{{P.FLEN-P.S_LEN{mvsgn}}, XE[P.S_LEN-1:0]},
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{{P.FLEN-P.D_LEN{mvsgn}}, XE[P.D_LEN-1:0]},
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XE, FmtE, SgnExtXE);
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mux4 #(1) sgnmux (XE[P.S_LEN-1], XE[P.D_LEN-1], XE[P.H_LEN-1], XE[P.LLEN-1], FmtE, mvsgn);
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mux3 #(P.FLEN) sgnextmux ({{P.FLEN-P.S_LEN{mvsgn}}, XE[P.S_LEN-1:0]},
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{{P.FLEN-P.D_LEN{mvsgn}}, XE[P.D_LEN-1:0]},
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{{P.FLEN-P.H_LEN{mvsgn}}, XE[P.H_LEN-1:0]},
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FmtE, SgnExtXE); // Q not needed because there is no fmv.x.q
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end
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// sign extend to XLEN if necessary
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if (P.FLEN>P.XLEN)
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assign IntSrcXE = SgnExtXE[P.XLEN-1:0];
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else
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@ -82,7 +82,7 @@ module cvtshiftcalc import cvw::*; #(parameter cvw_t P) (
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P.FMT: ResNegNF = -($clog2(P.NF)+1)'(P.NF);
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P.FMT1: ResNegNF = -($clog2(P.NF)+1)'(P.NF1);
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P.FMT2: ResNegNF = -($clog2(P.NF)+1)'(P.NF2);
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default: ResNegNF = 'x;
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default: ResNegNF = 0; // Not used for floating-point so don't care, but convert to unsigned long has OutFmt = 11.
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endcase
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end else if (P.FPSIZES == 4) begin
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@ -50,7 +50,7 @@ module fmashiftcalc import cvw::*; #(parameter cvw_t P) (
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// calculate the sum's exponent
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assign PreNormSumExp = FmaSe + {{P.NE+2-$unsigned($clog2(3*P.NF+5)){1'b1}}, ~FmaSCnt} + (P.NE+2)'(P.NF+3);
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//convert the sum's exponent into the proper percision
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//convert the sum's exponent into the proper precision
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if (P.FPSIZES == 1) begin
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assign NormSumExp = PreNormSumExp;
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end else if (P.FPSIZES == 2) begin
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@ -127,9 +127,9 @@ module postprocess import cvw::*; #(parameter cvw_t P) (
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assign InfIn = XInf|YInf|ZInf;
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assign NaNIn = XNaN|YNaN|ZNaN;
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// choose the ouptut format depending on the opperation
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// - fp -> fp: OpCtrl contains the percision of the output
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// - otherwise: Fmt contains the percision of the output
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// choose the output format depending on the opperation
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// - fp -> fp: OpCtrl contains the precision of the output
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// - otherwise: Fmt contains the precision of the output
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if (P.FPSIZES == 2)
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assign OutFmt = IntToFp|~CvtOp ? Fmt : (OpCtrl[1:0] == P.FMT);
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else if (P.FPSIZES == 3 | P.FPSIZES == 4)
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@ -145,18 +145,18 @@ module round import cvw::*; #(parameter cvw_t P) (
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end else if (P.FPSIZES == 3) begin
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// 1: XLEN > NF > NF1
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if (XLENPOS == 1) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF2-2:P.CORRSHIFTSZ-P.NF1-1]&FpRes&(OutFmt==P.FMT1)) |
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if (XLENPOS == 1) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF2-2:P.CORRSHIFTSZ-P.NF1-1]&FpRes&(OutFmt==P.FMT2)) |
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(|Mf[P.CORRSHIFTSZ-P.NF1-2:P.CORRSHIFTSZ-P.NF-1]&FpRes&~(OutFmt==P.FMT)) |
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(|Mf[P.CORRSHIFTSZ-P.NF-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes) |
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(|Mf[P.CORRSHIFTSZ-P.XLEN-2:0]);
|
||||
// 2: NF > XLEN > NF1
|
||||
if (XLENPOS == 2) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF2-2:P.CORRSHIFTSZ-P.NF1-1]&FpRes&(OutFmt==P.FMT1)) |
|
||||
if (XLENPOS == 2) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF2-2:P.CORRSHIFTSZ-P.NF1-1]&FpRes&(OutFmt==P.FMT2)) |
|
||||
(|Mf[P.CORRSHIFTSZ-P.NF1-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes&~(OutFmt==P.FMT)) |
|
||||
(|Mf[P.CORRSHIFTSZ-P.XLEN-2:P.CORRSHIFTSZ-P.NF-1]&(IntRes|~(OutFmt==P.FMT))) |
|
||||
(|Mf[P.CORRSHIFTSZ-P.NF-2:0]);
|
||||
// 3: NF > NF1 > XLEN
|
||||
if (XLENPOS == 3) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF2-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes&(OutFmt==P.FMT1)) |
|
||||
(|Mf[P.CORRSHIFTSZ-P.XLEN-2:P.CORRSHIFTSZ-P.NF1-1]&((OutFmt==P.FMT1)|IntRes)) |
|
||||
if (XLENPOS == 3) assign NormSticky = (|Mf[P.CORRSHIFTSZ-P.NF2-2:P.CORRSHIFTSZ-P.XLEN-1]&FpRes&(OutFmt==P.FMT2)) |
|
||||
(|Mf[P.CORRSHIFTSZ-P.XLEN-2:P.CORRSHIFTSZ-P.NF1-1]&((OutFmt==P.FMT2)|IntRes)) |
|
||||
(|Mf[P.CORRSHIFTSZ-P.NF1-2:P.CORRSHIFTSZ-P.NF-1]&(~(OutFmt==P.FMT)|IntRes)) |
|
||||
(|Mf[P.CORRSHIFTSZ-P.NF-2:0]);
|
||||
|
||||
|
|
|
|||
|
|
@ -232,95 +232,7 @@ module instrNameDecTB(
|
|||
10'b1000111_???: name = "FMSUB";
|
||||
10'b1001011_???: name = "FNMSUB";
|
||||
10'b1001111_???: name = "FNMADD";
|
||||
10'b1010011_000: if (funct7[6:2] == 5'b00000) name = "FADD";
|
||||
else if (funct7[6:2] == 5'b00001) name = "FSUB";
|
||||
else if (funct7[6:2] == 5'b00010) name = "FMUL";
|
||||
else if (funct7[6:2] == 5'b00011) name = "FDIV";
|
||||
else if (funct7[6:2] == 5'b01011) name = "FSQRT";
|
||||
else if (funct7 == 7'b1100000 & rs2 == 5'b00000) name = "FCVT.W.S";
|
||||
else if (funct7 == 7'b1100000 & rs2 == 5'b00001) name = "FCVT.WU.S";
|
||||
else if (funct7 == 7'b1100000 & rs2 == 5'b00010) name = "FCVT.L.S";
|
||||
else if (funct7 == 7'b1100000 & rs2 == 5'b00011) name = "FCVT.LU.S";
|
||||
else if (funct7 == 7'b1101000 & rs2 == 5'b00000) name = "FCVT.S.W";
|
||||
else if (funct7 == 7'b1101000 & rs2 == 5'b00001) name = "FCVT.S.WU";
|
||||
else if (funct7 == 7'b1101000 & rs2 == 5'b00010) name = "FCVT.S.L";
|
||||
else if (funct7 == 7'b1101000 & rs2 == 5'b00011) name = "FCVT.S.LU";
|
||||
else if (funct7 == 7'b1100001 & rs2 == 5'b00000) name = "FCVT.W.D";
|
||||
else if (funct7 == 7'b1100001 & rs2 == 5'b00001) name = "FCVT.WU.D";
|
||||
else if (funct7 == 7'b1100001 & rs2 == 5'b00010) name = "FCVT.L.D";
|
||||
else if (funct7 == 7'b1100001 & rs2 == 5'b00011) name = "FCVT.LU.D";
|
||||
else if (funct7 == 7'b1101001 & rs2 == 5'b00000) name = "FCVT.D.W";
|
||||
else if (funct7 == 7'b1101001 & rs2 == 5'b00001) name = "FCVT.D.WU";
|
||||
else if (funct7 == 7'b1101001 & rs2 == 5'b00010) name = "FCVT.D.L";
|
||||
else if (funct7 == 7'b1101001 & rs2 == 5'b00011) name = "FCVT.D.LU";
|
||||
else if (funct7 == 7'b0100000 & rs2 == 5'b00001) name = "FCVT.S.D";
|
||||
else if (funct7 == 7'b0100001 & rs2 == 5'b00000) name = "FCVT.D.S";
|
||||
else if (funct7 == 7'b1110000 & rs2 == 5'b00000) name = "FMV.X.W";
|
||||
else if (funct7 == 7'b1111000 & rs2 == 5'b00000) name = "FMV.W.X";
|
||||
else if (funct7 == 7'b1110001 & rs2 == 5'b00000) name = "FMV.X.D"; // DOUBLE
|
||||
else if (funct7 == 7'b1111001 & rs2 == 5'b00000) name = "FMV.D.X"; // DOUBLE
|
||||
else if (funct7[6:2] == 5'b00100) name = "FSGNJ";
|
||||
else if (funct7[6:2] == 5'b00101) name = "FMIN";
|
||||
else if (funct7[6:2] == 5'b10100) name = "FLE";
|
||||
else name = "ILLEGAL";
|
||||
10'b1010011_001: if (funct7[6:2] == 5'b00000) name = "FADD";
|
||||
else if (funct7[6:2] == 5'b00001) name = "FSUB";
|
||||
else if (funct7[6:2] == 5'b00010) name = "FMUL";
|
||||
else if (funct7[6:2] == 5'b00011) name = "FDIV";
|
||||
else if (funct7[6:2] == 5'b01011) name = "FSQRT";
|
||||
else if (funct7 == 7'b1100000 & rs2 == 5'b00000) name = "FCVT.W.S";
|
||||
else if (funct7 == 7'b1100000 & rs2 == 5'b00001) name = "FCVT.WU.S";
|
||||
else if (funct7 == 7'b1100000 & rs2 == 5'b00010) name = "FCVT.L.S";
|
||||
else if (funct7 == 7'b1100000 & rs2 == 5'b00011) name = "FCVT.LU.S";
|
||||
else if (funct7 == 7'b1101000 & rs2 == 5'b00000) name = "FCVT.S.W";
|
||||
else if (funct7 == 7'b1101000 & rs2 == 5'b00001) name = "FCVT.S.WU";
|
||||
else if (funct7 == 7'b1101000 & rs2 == 5'b00010) name = "FCVT.S.L";
|
||||
else if (funct7 == 7'b1101000 & rs2 == 5'b00011) name = "FCVT.S.LU";
|
||||
else if (funct7 == 7'b1100001 & rs2 == 5'b00000) name = "FCVT.W.D";
|
||||
else if (funct7 == 7'b1100001 & rs2 == 5'b00001) name = "FCVT.WU.D";
|
||||
else if (funct7 == 7'b1100001 & rs2 == 5'b00010) name = "FCVT.L.D";
|
||||
else if (funct7 == 7'b1100001 & rs2 == 5'b00011) name = "FCVT.LU.D";
|
||||
else if (funct7 == 7'b1101001 & rs2 == 5'b00000) name = "FCVT.D.W";
|
||||
else if (funct7 == 7'b1101001 & rs2 == 5'b00001) name = "FCVT.D.WU";
|
||||
else if (funct7 == 7'b1101001 & rs2 == 5'b00010) name = "FCVT.D.L";
|
||||
else if (funct7 == 7'b1101001 & rs2 == 5'b00011) name = "FCVT.D.LU";
|
||||
else if (funct7 == 7'b0100000 & rs2 == 5'b00001) name = "FCVT.S.D";
|
||||
else if (funct7 == 7'b0100001 & rs2 == 5'b00000) name = "FCVT.D.S";
|
||||
else if (funct7[6:2] == 5'b00100) name = "FSGNJN";
|
||||
else if (funct7[6:2] == 5'b00101) name = "FMAX";
|
||||
else if (funct7[6:2] == 5'b10100) name = "FLT";
|
||||
else if (funct7[6:2] == 5'b11100) name = "FCLASS";
|
||||
else name = "ILLEGAL";
|
||||
10'b1010011_010: if (funct7[6:2] == 5'b00000) name = "FADD";
|
||||
else if (funct7[6:2] == 5'b00001) name = "FSUB";
|
||||
else if (funct7[6:2] == 5'b00010) name = "FMUL";
|
||||
else if (funct7[6:2] == 5'b00011) name = "FDIV";
|
||||
else if (funct7[6:2] == 5'b01011) name = "FSQRT";
|
||||
else if (funct7 == 7'b1100000 & rs2 == 5'b00000) name = "FCVT.W.S";
|
||||
else if (funct7 == 7'b1100000 & rs2 == 5'b00001) name = "FCVT.WU.S";
|
||||
else if (funct7 == 7'b1100000 & rs2 == 5'b00010) name = "FCVT.L.S";
|
||||
else if (funct7 == 7'b1100000 & rs2 == 5'b00011) name = "FCVT.LU.S";
|
||||
else if (funct7 == 7'b1101000 & rs2 == 5'b00000) name = "FCVT.S.W";
|
||||
else if (funct7 == 7'b1101000 & rs2 == 5'b00001) name = "FCVT.S.WU";
|
||||
else if (funct7 == 7'b1101000 & rs2 == 5'b00010) name = "FCVT.S.L";
|
||||
else if (funct7 == 7'b1101000 & rs2 == 5'b00011) name = "FCVT.S.LU";
|
||||
else if (funct7 == 7'b1100001 & rs2 == 5'b00000) name = "FCVT.W.D";
|
||||
else if (funct7 == 7'b1100001 & rs2 == 5'b00001) name = "FCVT.WU.D";
|
||||
else if (funct7 == 7'b1100001 & rs2 == 5'b00010) name = "FCVT.L.D";
|
||||
else if (funct7 == 7'b1100001 & rs2 == 5'b00011) name = "FCVT.LU.D";
|
||||
else if (funct7 == 7'b1101001 & rs2 == 5'b00000) name = "FCVT.D.W";
|
||||
else if (funct7 == 7'b1101001 & rs2 == 5'b00001) name = "FCVT.D.WU";
|
||||
else if (funct7 == 7'b1101001 & rs2 == 5'b00010) name = "FCVT.D.L";
|
||||
else if (funct7 == 7'b1101001 & rs2 == 5'b00011) name = "FCVT.D.LU";
|
||||
else if (funct7 == 7'b0100000 & rs2 == 5'b00001) name = "FCVT.S.D";
|
||||
else if (funct7 == 7'b0100001 & rs2 == 5'b00000) name = "FCVT.D.S";
|
||||
else if (funct7[6:2] == 5'b00100) name = "FSGNJX";
|
||||
else if (funct7[6:2] == 5'b10100) name = "FEQ";
|
||||
else name = "ILLEGAL";
|
||||
/* verilator lint_off CASEOVERLAP */
|
||||
// *** RT: definitely take a look at this. This overlaps with 10'b1010011_000
|
||||
10'b1010011_???: if (funct7[6:2] == 5'b00000) name = "FADD";
|
||||
/* verilator lint_on CASEOVERLAP */
|
||||
else if (funct7[6:2] == 5'b00001) name = "FSUB";
|
||||
else if (funct7[6:2] == 5'b00010) name = "FMUL";
|
||||
else if (funct7[6:2] == 5'b00011) name = "FDIV";
|
||||
|
|
@ -343,6 +255,49 @@ module instrNameDecTB(
|
|||
else if (funct7 == 7'b1101001 & rs2 == 5'b00011) name = "FCVT.D.LU";
|
||||
else if (funct7 == 7'b0100000 & rs2 == 5'b00001) name = "FCVT.S.D";
|
||||
else if (funct7 == 7'b0100001 & rs2 == 5'b00000) name = "FCVT.D.S";
|
||||
else if (funct7 == 7'b1100010 & rs2 == 5'b00000) name = "FCVT.W.H";
|
||||
else if (funct7 == 7'b1100010 & rs2 == 5'b00001) name = "FCVT.WU.H";
|
||||
else if (funct7 == 7'b1100010 & rs2 == 5'b00010) name = "FCVT.L.H";
|
||||
else if (funct7 == 7'b1100010 & rs2 == 5'b00011) name = "FCVT.LU.H";
|
||||
else if (funct7 == 7'b1101010 & rs2 == 5'b00000) name = "FCVT.H.W";
|
||||
else if (funct7 == 7'b1101010 & rs2 == 5'b00001) name = "FCVT.H.WU";
|
||||
else if (funct7 == 7'b1101010 & rs2 == 5'b00010) name = "FCVT.H.L";
|
||||
else if (funct7 == 7'b1101010 & rs2 == 5'b00011) name = "FCVT.H.LU";
|
||||
else if (funct7 == 7'b1100011 & rs2 == 5'b00000) name = "FCVT.W.Q";
|
||||
else if (funct7 == 7'b1100011 & rs2 == 5'b00001) name = "FCVT.WU.Q";
|
||||
else if (funct7 == 7'b1100011 & rs2 == 5'b00010) name = "FCVT.L.Q";
|
||||
else if (funct7 == 7'b1100011 & rs2 == 5'b00011) name = "FCVT.LU.Q";
|
||||
else if (funct7 == 7'b1101011 & rs2 == 5'b00000) name = "FCVT.Q.W";
|
||||
else if (funct7 == 7'b1101011 & rs2 == 5'b00001) name = "FCVT.Q.WU";
|
||||
else if (funct7 == 7'b1101011 & rs2 == 5'b00010) name = "FCVT.Q.L";
|
||||
else if (funct7 == 7'b1101011 & rs2 == 5'b00011) name = "FCVT.Q.LU";
|
||||
else if (funct7 == 7'b0100000 & rs2 == 5'b00001) name = "FCVT.S.D";
|
||||
else if (funct7 == 7'b0100000 & rs2 == 5'b00010) name = "FCVT.S.H";
|
||||
else if (funct7 == 7'b0100000 & rs2 == 5'b00011) name = "FCVT.S.Q";
|
||||
else if (funct7 == 7'b0100001 & rs2 == 5'b00000) name = "FCVT.D.S";
|
||||
else if (funct7 == 7'b0100001 & rs2 == 5'b00010) name = "FCVT.D.H";
|
||||
else if (funct7 == 7'b0100001 & rs2 == 5'b00011) name = "FCVT.D.Q";
|
||||
else if (funct7 == 7'b0100010 & rs2 == 5'b00000) name = "FCVT.H.S";
|
||||
else if (funct7 == 7'b0100010 & rs2 == 5'b00001) name = "FCVT.H.D";
|
||||
else if (funct7 == 7'b0100010 & rs2 == 5'b00011) name = "FCVT.H.Q";
|
||||
else if (funct7 == 7'b0100011 & rs2 == 5'b00000) name = "FCVT.Q.S";
|
||||
else if (funct7 == 7'b0100011 & rs2 == 5'b00001) name = "FCVT.Q.D";
|
||||
else if (funct7 == 7'b0100011 & rs2 == 5'b00010) name = "FCVT.Q.H";
|
||||
else if (funct7 == 7'b1110000 & rs2 == 5'b00000 & funct3 == 3'b000) name = "FMV.X.W";
|
||||
else if (funct7 == 7'b1111000 & rs2 == 5'b00000 & funct3 == 3'b000) name = "FMV.W.X";
|
||||
else if (funct7 == 7'b1110001 & rs2 == 5'b00000 & funct3 == 3'b000) name = "FMV.X.D";
|
||||
else if (funct7 == 7'b1111001 & rs2 == 5'b00000 & funct3 == 3'b000) name = "FMV.D.X";
|
||||
else if (funct7 == 7'b1110010 & rs2 == 5'b00000 & funct3 == 3'b000) name = "FMV.X.H";
|
||||
else if (funct7 == 7'b1111010 & rs2 == 5'b00000 & funct3 == 3'b000) name = "FMV.H.X";
|
||||
else if (funct7[6:2] == 5'b00100 & funct3 == 3'b000) name = "FSGNJ";
|
||||
else if (funct7[6:2] == 5'b00101 & funct3 == 3'b000) name = "FMIN";
|
||||
else if (funct7[6:2] == 5'b10100 & funct3 == 3'b000) name = "FLE";
|
||||
else if (funct7[6:2] == 5'b00100 & funct3 == 3'b001) name = "FSGNJN";
|
||||
else if (funct7[6:2] == 5'b00101 & funct3 == 3'b001) name = "FMAX";
|
||||
else if (funct7[6:2] == 5'b10100 & funct3 == 3'b001) name = "FLT";
|
||||
else if (funct7[6:2] == 5'b11100 & funct3 == 3'b001) name = "FCLASS";
|
||||
else if (funct7[6:2] == 5'b00100 & funct3 == 3'b010) name = "FSGNJX";
|
||||
else if (funct7[6:2] == 5'b10100 & funct3 == 3'b010) name = "FEQ";
|
||||
else name = "ILLEGAL";
|
||||
10'b0000111_010: name = "FLW";
|
||||
10'b0100111_010: name = "FSW";
|
||||
|
|
|
|||
|
|
@ -882,7 +882,7 @@ module testbenchfp;
|
|||
// - the sign of the NaN does not matter for the opperations being tested
|
||||
// - when 2 or more NaNs are inputed the NaN that is propigated doesn't matter
|
||||
if (UnitVal !== `CVTFPUNIT & UnitVal !== `CVTINTUNIT)
|
||||
case (FmtVal)
|
||||
case (FmtVal)
|
||||
2'b11: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res === {1'b0, {P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) |
|
||||
(AnsFlg[4]&(Res[P.Q_LEN-2:0] === {{P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) |
|
||||
(XNaN&(Res[P.Q_LEN-2:0] === {X[P.Q_LEN-2:P.Q_NF],1'b1,X[P.Q_NF-2:0]})) |
|
||||
|
|
@ -903,9 +903,9 @@ module testbenchfp;
|
|||
(XNaN&(Res[P.H_LEN-2:0] === {X[P.H_LEN-2:P.H_NF],1'b1,X[P.H_NF-2:0]})) |
|
||||
(YNaN&(Res[P.H_LEN-2:0] === {Y[P.H_LEN-2:P.H_NF],1'b1,Y[P.H_NF-2:0]})) |
|
||||
(ZNaN&(Res[P.H_LEN-2:0] === {Z[P.H_LEN-2:P.H_NF],1'b1,Z[P.H_NF-2:0]})));
|
||||
endcase
|
||||
else if (UnitVal === `CVTFPUNIT) // if converting from floating point to floating point OpCtrl contains the final FP format
|
||||
case (OpCtrlVal[1:0])
|
||||
endcase
|
||||
else if (UnitVal === `CVTFPUNIT) // if converting from floating point to floating point OpCtrl contains the final FP format
|
||||
case (OpCtrlVal[1:0])
|
||||
2'b11: NaNGood = (((P.IEEE754==0)&AnsNaN&(Res === {1'b0, {P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) |
|
||||
(AnsFlg[4]&(Res[P.Q_LEN-2:0] === {{P.Q_NE+1{1'b1}}, {P.Q_NF-1{1'b0}}})) |
|
||||
(AnsNaN&(Res[P.Q_LEN-2:0] === Ans[P.Q_LEN-2:0])) |
|
||||
|
|
@ -926,72 +926,70 @@ module testbenchfp;
|
|||
(AnsNaN&(Res[P.H_LEN-2:0] === Ans[P.H_LEN-2:0])) |
|
||||
(XNaN&(Res[P.H_LEN-2:0] === {X[P.H_LEN-2:P.H_NF],1'b1,X[P.H_NF-2:0]})) |
|
||||
(YNaN&(Res[P.H_LEN-2:0] === {Y[P.H_LEN-2:P.H_NF],1'b1,Y[P.H_NF-2:0]})));
|
||||
endcase
|
||||
else NaNGood = 1'b0; // integers can't be NaNs
|
||||
endcase
|
||||
else NaNGood = 1'b0; // integers can't be NaNs
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// ||||||| ||| ||| ||||||| ||||||| ||| |||
|
||||
// ||| ||| ||| ||| ||| ||| |||
|
||||
// ||| |||||||||| ||||||| ||| ||||||
|
||||
// ||| ||| ||| ||| ||| ||| |||
|
||||
// ||||||| ||| ||| ||||||| ||||||| ||| |||
|
||||
// ||||||| ||| ||| ||||||| ||||||| ||| |||
|
||||
// ||| ||| ||| ||| ||| ||| |||
|
||||
// ||| |||||||||| ||||||| ||| ||||||
|
||||
// ||| ||| ||| ||| ||| ||| |||
|
||||
// ||||||| ||| ||| ||||||| ||||||| ||| |||
|
||||
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// check if result is correct
|
||||
// wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage)
|
||||
assign ResMatch = ((Res === Ans) | NaNGood | (NaNGood === 1'bx));
|
||||
assign FlagMatch = ((ResFlg === AnsFlg) | (AnsFlg === 5'bx));
|
||||
assign divsqrtop = (OpCtrlVal == `SQRT_OPCTRL) | (OpCtrlVal == `DIV_OPCTRL);
|
||||
assign FMAop = (OpCtrlVal == `FMAUNIT);
|
||||
assign DivDone = OldFDivBusyE & ~FDivBusyE;
|
||||
// check if result is correct
|
||||
// wait till the division result is done or one extra cylcle for early termination (to simulate the EM pipline stage)
|
||||
assign ResMatch = ((Res === Ans) | NaNGood | (NaNGood === 1'bx));
|
||||
assign FlagMatch = ((ResFlg === AnsFlg) | (AnsFlg === 5'bx));
|
||||
assign divsqrtop = (OpCtrlVal == `SQRT_OPCTRL) | (OpCtrlVal == `DIV_OPCTRL);
|
||||
assign FMAop = (OpCtrlVal == `FMAUNIT);
|
||||
assign DivDone = OldFDivBusyE & ~FDivBusyE;
|
||||
|
||||
// Maybe change OpCtrl but for now just look at TEST for fma test
|
||||
assign CheckNow = ((DivDone | ~divsqrtop) | (TEST == "add" | TEST == "fma" | TEST == "sub")) & (UnitVal !== `CVTINTUNIT) & (UnitVal !== `CMPUNIT);
|
||||
if (~(ResMatch & FlagMatch) & CheckNow) begin
|
||||
// Maybe change OpCtrl but for now just look at TEST for fma test
|
||||
assign CheckNow = ((DivDone | ~divsqrtop) | (TEST == "add" | TEST == "fma" | TEST == "sub")) & (UnitVal !== `CVTINTUNIT) & (UnitVal !== `CMPUNIT);
|
||||
if (~(ResMatch & FlagMatch) & CheckNow) begin
|
||||
errors += 1;
|
||||
$display("\nError in %s", Tests[TestNum]);
|
||||
$display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]);
|
||||
$display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
|
||||
$stop;
|
||||
end else if (((UnitVal === `CVTINTUNIT) | (UnitVal === `CMPUNIT)) &
|
||||
~(ResMatch & FlagMatch) & (Ans[0] !== 1'bx)) begin // Check for conversion and comparisons
|
||||
errors += 1;
|
||||
$display("\nError in %s", Tests[TestNum]);
|
||||
$display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]);
|
||||
$display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Expected: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
|
||||
$display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]);
|
||||
$display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
|
||||
$stop;
|
||||
end else if (((UnitVal === `CVTINTUNIT) | (UnitVal === `CMPUNIT)) &
|
||||
~(ResMatch & FlagMatch) & (Ans[0] !== 1'bx)) begin // Check for conversion and comparisons
|
||||
errors += 1;
|
||||
$display("\nError in %s", Tests[TestNum]);
|
||||
$display("TestNum %d OpCtrl %d", TestNum, OpCtrl[TestNum]);
|
||||
$display("inputs: %h %h %h\nSrcA: %h\n Res: %h %h\n Ans: %h %h", X, Y, Z, SrcA, Res, ResFlg, Ans, AnsFlg);
|
||||
$stop;
|
||||
end
|
||||
end
|
||||
|
||||
if (TestVectors[VectorNum][0] === 1'bx & Tests[TestNum] !== "") begin // if reached the eof
|
||||
// increment the test
|
||||
TestNum += 1;
|
||||
// clear the vectors
|
||||
for(int i=0; i<6133248; i++) TestVectors[i] = {P.FLEN*4+8{1'bx}};
|
||||
// read next files
|
||||
$readmemh({`PATH, Tests[TestNum]}, TestVectors);
|
||||
// set the vector index back to 0
|
||||
VectorNum = 0;
|
||||
// incemet the operation if all the rounding modes have been tested
|
||||
if (FrmNum === 4) OpCtrlNum += 1;
|
||||
// increment the rounding mode or loop back to rne
|
||||
if (FrmNum < 4)
|
||||
FrmNum += 1;
|
||||
else begin
|
||||
FrmNum = 0;
|
||||
// Add some time as a buffer between tests at the end of each test
|
||||
repeat (10)
|
||||
@(posedge clk);
|
||||
end
|
||||
// if no more Tests - finish
|
||||
if (Tests[TestNum] === "") begin
|
||||
$display("\nAll Tests completed with %d errors\n", errors);
|
||||
$stop;
|
||||
end
|
||||
$display("Running %s vectors", Tests[TestNum]);
|
||||
// increment the test
|
||||
TestNum += 1;
|
||||
// clear the vectors
|
||||
for(int i=0; i<6133248; i++) TestVectors[i] = {P.FLEN*4+8{1'bx}};
|
||||
// read next files
|
||||
$readmemh({`PATH, Tests[TestNum]}, TestVectors);
|
||||
// set the vector index back to 0
|
||||
VectorNum = 0;
|
||||
// incemet the operation if all the rounding modes have been tested
|
||||
if (FrmNum === 4) OpCtrlNum += 1;
|
||||
// increment the rounding mode or loop back to rne
|
||||
if (FrmNum < 4) FrmNum += 1;
|
||||
else begin
|
||||
FrmNum = 0;
|
||||
// Add some time as a buffer between tests at the end of each test
|
||||
repeat (10)
|
||||
@(posedge clk);
|
||||
end
|
||||
// if no more Tests - finish
|
||||
if (Tests[TestNum] === "") begin
|
||||
$display("\nAll Tests completed with %d errors\n", errors);
|
||||
$stop;
|
||||
end
|
||||
$display("Running %s vectors", Tests[TestNum]);
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -127,6 +127,8 @@ module testbench;
|
|||
"arch64zbs": if (P.ZBS_SUPPORTED) tests = arch64zbs;
|
||||
"arch64zicboz": if (P.ZICBOZ_SUPPORTED) tests = arch64zicboz;
|
||||
"arch64zcb": if (P.ZCB_SUPPORTED) tests = arch64zcb;
|
||||
"arch64zfh": if (P.ZFH_SUPPORTED) tests = arch64zfh;
|
||||
// "arch64zfa": if (P.ZFA_SUPPORTED) tests = arch64zfa;
|
||||
endcase
|
||||
end else begin // RV32
|
||||
case (TEST)
|
||||
|
|
@ -161,6 +163,8 @@ module testbench;
|
|||
"arch32zbs": if (P.ZBS_SUPPORTED) tests = arch32zbs;
|
||||
"arch32zicboz": if (P.ZICBOZ_SUPPORTED) tests = arch32zicboz;
|
||||
"arch32zcb": if (P.ZCB_SUPPORTED) tests = arch32zcb;
|
||||
"arch32zfh": if (P.ZFH_SUPPORTED) tests = arch32zfh;
|
||||
"arch32zfaf": if (P.ZFA_SUPPORTED) tests = arch32zfaf;
|
||||
endcase
|
||||
end
|
||||
if (tests.size() == 0) begin
|
||||
|
|
|
|||
|
|
@ -1291,6 +1291,123 @@ string imperas32f[] = '{
|
|||
"rv64i_m/F/src/fsw-align-01.S"
|
||||
};
|
||||
|
||||
string arch64zfh[] = '{
|
||||
`RISCVARCHTEST,
|
||||
"rv64i_m/Zfh/src/fadd_b10-01.S",
|
||||
"rv64i_m/Zfh/src/fadd_b1-01.S",
|
||||
"rv64i_m/Zfh/src/fadd_b11-01.S",
|
||||
"rv64i_m/Zfh/src/fadd_b12-01.S",
|
||||
"rv64i_m/Zfh/src/fadd_b13-01.S",
|
||||
"rv64i_m/Zfh/src/fadd_b2-01.S",
|
||||
"rv64i_m/Zfh/src/fadd_b3-01.S",
|
||||
"rv64i_m/Zfh/src/fadd_b4-01.S",
|
||||
"rv64i_m/Zfh/src/fadd_b5-01.S",
|
||||
"rv64i_m/Zfh/src/fadd_b7-01.S",
|
||||
"rv64i_m/Zfh/src/fadd_b8-01.S",
|
||||
"rv64i_m/Zfh/src/fclass_b1-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.h.w_b25-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.h.w_b26-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.h.wu_b25-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.h.wu_b26-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.w.h_b1-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.w.h_b22-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.w.h_b23-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.w.h_b24-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.w.h_b27-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.w.h_b28-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.w.h_b29-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.wu.h_b1-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.wu.h_b22-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.wu.h_b23-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.wu.h_b24-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.wu.h_b27-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.wu.h_b28-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.wu.h_b29-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.h.l_b25-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.h.l_b26-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.h.lu_b25-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.h.lu_b26-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.l.h_b1-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.l.h_b22-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.l.h_b23-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.l.h_b24-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.l.h_b27-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.l.h_b28-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.l.h_b29-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.lu.h_b1-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.lu.h_b22-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.lu.h_b23-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.lu.h_b24-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.lu.h_b27-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.lu.h_b28-01.S",
|
||||
"rv64i_m/Zfh/src/fcvt.lu.h_b29-01.S",
|
||||
"rv64i_m/Zfh/src/fdiv_b20-01.S",
|
||||
"rv64i_m/Zfh/src/fdiv_b1-01.S",
|
||||
"rv64i_m/Zfh/src/fdiv_b2-01.S",
|
||||
"rv64i_m/Zfh/src/fdiv_b21-01.S",
|
||||
"rv64i_m/Zfh/src/fdiv_b3-01.S",
|
||||
"rv64i_m/Zfh/src/fdiv_b4-01.S",
|
||||
"rv64i_m/Zfh/src/fdiv_b5-01.S",
|
||||
"rv64i_m/Zfh/src/fdiv_b6-01.S",
|
||||
"rv64i_m/Zfh/src/fdiv_b7-01.S",
|
||||
"rv64i_m/Zfh/src/fdiv_b8-01.S",
|
||||
"rv64i_m/Zfh/src/fdiv_b9-01.S",
|
||||
"rv64i_m/Zfh/src/feq_b1-01.S",
|
||||
"rv64i_m/Zfh/src/feq_b19-01.S",
|
||||
"rv64i_m/Zfh/src/fle_b1-01.S",
|
||||
"rv64i_m/Zfh/src/fle_b19-01.S",
|
||||
"rv64i_m/Zfh/src/flt_b1-01.S",
|
||||
"rv64i_m/Zfh/src/flt_b19-01.S",
|
||||
"rv64i_m/Zfh/src/flh-align-01.S",
|
||||
"rv64i_m/Zfh/src/fmax_b1-01.S",
|
||||
"rv64i_m/Zfh/src/fmax_b19-01.S",
|
||||
"rv64i_m/Zfh/src/fmin_b1-01.S",
|
||||
"rv64i_m/Zfh/src/fmin_b19-01.S",
|
||||
"rv64i_m/Zfh/src/fmul_b1-01.S",
|
||||
"rv64i_m/Zfh/src/fmul_b2-01.S",
|
||||
"rv64i_m/Zfh/src/fmul_b3-01.S",
|
||||
"rv64i_m/Zfh/src/fmul_b4-01.S",
|
||||
"rv64i_m/Zfh/src/fmul_b5-01.S",
|
||||
"rv64i_m/Zfh/src/fmul_b6-01.S",
|
||||
"rv64i_m/Zfh/src/fmul_b7-01.S",
|
||||
"rv64i_m/Zfh/src/fmul_b8-01.S",
|
||||
"rv64i_m/Zfh/src/fmul_b9-01.S",
|
||||
"rv64i_m/Zfh/src/fmv.h.x_b25-01.S",
|
||||
"rv64i_m/Zfh/src/fmv.h.x_b26-01.S",
|
||||
"rv64i_m/Zfh/src/fmv.x.h_b1-01.S",
|
||||
"rv64i_m/Zfh/src/fmv.x.h_b22-01.S",
|
||||
"rv64i_m/Zfh/src/fmv.x.h_b23-01.S",
|
||||
"rv64i_m/Zfh/src/fmv.x.h_b24-01.S",
|
||||
"rv64i_m/Zfh/src/fmv.x.h_b27-01.S",
|
||||
"rv64i_m/Zfh/src/fmv.x.h_b28-01.S",
|
||||
"rv64i_m/Zfh/src/fmv.x.h_b29-01.S",
|
||||
"rv64i_m/Zfh/src/fsgnj_b1-01.S",
|
||||
"rv64i_m/Zfh/src/fsgnjn_b1-01.S",
|
||||
"rv64i_m/Zfh/src/fsgnjx_b1-01.S",
|
||||
"rv64i_m/Zfh/src/fsqrt_b1-01.S",
|
||||
"rv64i_m/Zfh/src/fsqrt_b20-01.S",
|
||||
"rv64i_m/Zfh/src/fsqrt_b2-01.S",
|
||||
"rv64i_m/Zfh/src/fsqrt_b3-01.S",
|
||||
"rv64i_m/Zfh/src/fsqrt_b4-01.S",
|
||||
"rv64i_m/Zfh/src/fsqrt_b5-01.S",
|
||||
"rv64i_m/Zfh/src/fsqrt_b7-01.S",
|
||||
"rv64i_m/Zfh/src/fsqrt_b8-01.S",
|
||||
"rv64i_m/Zfh/src/fsqrt_b9-01.S",
|
||||
"rv64i_m/Zfh/src/fsub_b10-01.S",
|
||||
"rv64i_m/Zfh/src/fsub_b1-01.S",
|
||||
"rv64i_m/Zfh/src/fsub_b11-01.S",
|
||||
"rv64i_m/Zfh/src/fsub_b12-01.S",
|
||||
"rv64i_m/Zfh/src/fsub_b13-01.S",
|
||||
"rv64i_m/Zfh/src/fsub_b2-01.S",
|
||||
"rv64i_m/Zfh/src/fsub_b3-01.S",
|
||||
"rv64i_m/Zfh/src/fsub_b4-01.S",
|
||||
"rv64i_m/Zfh/src/fsub_b5-01.S",
|
||||
"rv64i_m/Zfh/src/fsub_b7-01.S",
|
||||
"rv64i_m/Zfh/src/fsub_b8-01.S",
|
||||
"rv64i_m/Zfh/src/fsh-align-01.S"
|
||||
};
|
||||
|
||||
|
||||
string arch64d_fma[] = '{
|
||||
`RISCVARCHTEST,
|
||||
//"rv64i_m/D/src/fmadd.d_b15-01.S",
|
||||
|
|
@ -1638,7 +1755,6 @@ string arch64zbs[] = '{
|
|||
|
||||
string arch32f[] = '{
|
||||
`RISCVARCHTEST,
|
||||
"rv32i_m/F/src/fdiv_b20-01.S",
|
||||
"rv32i_m/F/src/fadd_b10-01.S",
|
||||
"rv32i_m/F/src/fadd_b1-01.S",
|
||||
"rv32i_m/F/src/fadd_b11-01.S",
|
||||
|
|
@ -1783,6 +1899,118 @@ string arch64zbs[] = '{
|
|||
"rv32i_m/F/src/fsw-align-01.S"
|
||||
};
|
||||
|
||||
string arch32zfh[] = '{
|
||||
`RISCVARCHTEST,
|
||||
"rv32i_m/Zfh/src/fadd_b10-01.S",
|
||||
"rv32i_m/Zfh/src/fadd_b1-01.S",
|
||||
"rv32i_m/Zfh/src/fadd_b11-01.S",
|
||||
"rv32i_m/Zfh/src/fadd_b12-01.S",
|
||||
"rv32i_m/Zfh/src/fadd_b13-01.S",
|
||||
"rv32i_m/Zfh/src/fadd_b2-01.S",
|
||||
"rv32i_m/Zfh/src/fadd_b3-01.S",
|
||||
"rv32i_m/Zfh/src/fadd_b4-01.S",
|
||||
"rv32i_m/Zfh/src/fadd_b5-01.S",
|
||||
"rv32i_m/Zfh/src/fadd_b7-01.S",
|
||||
"rv32i_m/Zfh/src/fadd_b8-01.S",
|
||||
"rv32i_m/Zfh/src/fclass_b1-01.S",
|
||||
"rv32i_m/Zfh/src/fcvt.h.w_b25-01.S",
|
||||
"rv32i_m/Zfh/src/fcvt.h.w_b26-01.S",
|
||||
"rv32i_m/Zfh/src/fcvt.h.wu_b25-01.S",
|
||||
"rv32i_m/Zfh/src/fcvt.h.wu_b26-01.S",
|
||||
"rv32i_m/Zfh/src/fcvt.w.h_b1-01.S",
|
||||
"rv32i_m/Zfh/src/fcvt.w.h_b22-01.S",
|
||||
"rv32i_m/Zfh/src/fcvt.w.h_b23-01.S",
|
||||
"rv32i_m/Zfh/src/fcvt.w.h_b24-01.S",
|
||||
"rv32i_m/Zfh/src/fcvt.w.h_b27-01.S",
|
||||
"rv32i_m/Zfh/src/fcvt.w.h_b28-01.S",
|
||||
"rv32i_m/Zfh/src/fcvt.w.h_b29-01.S",
|
||||
"rv32i_m/Zfh/src/fcvt.wu.h_b1-01.S",
|
||||
"rv32i_m/Zfh/src/fcvt.wu.h_b22-01.S",
|
||||
"rv32i_m/Zfh/src/fcvt.wu.h_b23-01.S",
|
||||
"rv32i_m/Zfh/src/fcvt.wu.h_b24-01.S",
|
||||
"rv32i_m/Zfh/src/fcvt.wu.h_b27-01.S",
|
||||
"rv32i_m/Zfh/src/fcvt.wu.h_b28-01.S",
|
||||
"rv32i_m/Zfh/src/fcvt.wu.h_b29-01.S",
|
||||
"rv32i_m/Zfh/src/fdiv_b20-01.S",
|
||||
"rv32i_m/Zfh/src/fdiv_b1-01.S",
|
||||
"rv32i_m/Zfh/src/fdiv_b2-01.S",
|
||||
"rv32i_m/Zfh/src/fdiv_b21-01.S",
|
||||
"rv32i_m/Zfh/src/fdiv_b3-01.S",
|
||||
"rv32i_m/Zfh/src/fdiv_b4-01.S",
|
||||
"rv32i_m/Zfh/src/fdiv_b5-01.S",
|
||||
"rv32i_m/Zfh/src/fdiv_b6-01.S",
|
||||
"rv32i_m/Zfh/src/fdiv_b7-01.S",
|
||||
"rv32i_m/Zfh/src/fdiv_b8-01.S",
|
||||
"rv32i_m/Zfh/src/fdiv_b9-01.S",
|
||||
"rv32i_m/Zfh/src/feq_b1-01.S",
|
||||
"rv32i_m/Zfh/src/feq_b19-01.S",
|
||||
"rv32i_m/Zfh/src/fle_b1-01.S",
|
||||
"rv32i_m/Zfh/src/fle_b19-01.S",
|
||||
"rv32i_m/Zfh/src/flt_b1-01.S",
|
||||
"rv32i_m/Zfh/src/flt_b19-01.S",
|
||||
"rv32i_m/Zfh/src/flh-align-01.S",
|
||||
"rv32i_m/Zfh/src/fmax_b1-01.S",
|
||||
"rv32i_m/Zfh/src/fmax_b19-01.S",
|
||||
"rv32i_m/Zfh/src/fmin_b1-01.S",
|
||||
"rv32i_m/Zfh/src/fmin_b19-01.S",
|
||||
"rv32i_m/Zfh/src/fmul_b1-01.S",
|
||||
"rv32i_m/Zfh/src/fmul_b2-01.S",
|
||||
"rv32i_m/Zfh/src/fmul_b3-01.S",
|
||||
"rv32i_m/Zfh/src/fmul_b4-01.S",
|
||||
"rv32i_m/Zfh/src/fmul_b5-01.S",
|
||||
"rv32i_m/Zfh/src/fmul_b6-01.S",
|
||||
"rv32i_m/Zfh/src/fmul_b7-01.S",
|
||||
"rv32i_m/Zfh/src/fmul_b8-01.S",
|
||||
"rv32i_m/Zfh/src/fmul_b9-01.S",
|
||||
"rv32i_m/Zfh/src/fmv.h.x_b25-01.S",
|
||||
"rv32i_m/Zfh/src/fmv.h.x_b26-01.S",
|
||||
"rv32i_m/Zfh/src/fmv.x.h_b1-01.S",
|
||||
"rv32i_m/Zfh/src/fmv.x.h_b22-01.S",
|
||||
"rv32i_m/Zfh/src/fmv.x.h_b23-01.S",
|
||||
"rv32i_m/Zfh/src/fmv.x.h_b24-01.S",
|
||||
"rv32i_m/Zfh/src/fmv.x.h_b27-01.S",
|
||||
"rv32i_m/Zfh/src/fmv.x.h_b28-01.S",
|
||||
"rv32i_m/Zfh/src/fmv.x.h_b29-01.S",
|
||||
"rv32i_m/Zfh/src/fsgnj_b1-01.S",
|
||||
"rv32i_m/Zfh/src/fsgnjn_b1-01.S",
|
||||
"rv32i_m/Zfh/src/fsgnjx_b1-01.S",
|
||||
"rv32i_m/Zfh/src/fsqrt_b1-01.S",
|
||||
"rv32i_m/Zfh/src/fsqrt_b20-01.S",
|
||||
"rv32i_m/Zfh/src/fsqrt_b2-01.S",
|
||||
"rv32i_m/Zfh/src/fsqrt_b3-01.S",
|
||||
"rv32i_m/Zfh/src/fsqrt_b4-01.S",
|
||||
"rv32i_m/Zfh/src/fsqrt_b5-01.S",
|
||||
"rv32i_m/Zfh/src/fsqrt_b7-01.S",
|
||||
"rv32i_m/Zfh/src/fsqrt_b8-01.S",
|
||||
"rv32i_m/Zfh/src/fsqrt_b9-01.S",
|
||||
"rv32i_m/Zfh/src/fsub_b10-01.S",
|
||||
"rv32i_m/Zfh/src/fsub_b1-01.S",
|
||||
"rv32i_m/Zfh/src/fsub_b11-01.S",
|
||||
"rv32i_m/Zfh/src/fsub_b12-01.S",
|
||||
"rv32i_m/Zfh/src/fsub_b13-01.S",
|
||||
"rv32i_m/Zfh/src/fsub_b2-01.S",
|
||||
"rv32i_m/Zfh/src/fsub_b3-01.S",
|
||||
"rv32i_m/Zfh/src/fsub_b4-01.S",
|
||||
"rv32i_m/Zfh/src/fsub_b5-01.S",
|
||||
"rv32i_m/Zfh/src/fsub_b7-01.S",
|
||||
"rv32i_m/Zfh/src/fsub_b8-01.S",
|
||||
"rv32i_m/Zfh/src/fsh-align-01.S"
|
||||
};
|
||||
|
||||
string arch32zfaf[] = '{
|
||||
`RISCVARCHTEST,
|
||||
"rv32i_m/F_Zfa/src/fle_b1-01.S",
|
||||
"rv32i_m/F_Zfa/src/fle_b19-01.S",
|
||||
"rv32i_m/F_Zfa/src/fli_b1-01.S",
|
||||
"rv32i_m/F_Zfa/src/fltq_b1-01.S",
|
||||
"rv32i_m/F_Zfa/src/fltq_b19-01.S",
|
||||
"rv32i_m/F_Zfa/src/fmin_b1-01.S",
|
||||
"rv32i_m/F_Zfa/src/fmin_b19-01.S",
|
||||
"rv32i_m/F_Zfa/src/fmax_b1-01.S",
|
||||
"rv32i_m/F_Zfa/src/fmax_b19-01.S",
|
||||
"rv32i_m/F_Zfa/src/fround_b1-01.S"
|
||||
};
|
||||
|
||||
string arch32d_fma[] = '{
|
||||
`RISCVARCHTEST,
|
||||
//"rv32i_m/D/src/fmadd.d_b15-01.S",
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue