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Full priv code coverage

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This commit is contained in:
Corey Hickson 2025-04-17 02:05:35 -07:00
parent 42f78c645b
commit f7bc15eb3e
2 changed files with 18 additions and 0 deletions
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6
sim/questa/coverage-exclusions-rv64gc.do
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@ -451,6 +451,12 @@ coverage exclude -scope /dut/core/priv/priv/csr/csru/csru -linerange [GetLineNum
coverage exclude -scope /dut/core/priv/priv/csr/counters/counters/cntr[1] -linerange [GetLineNum ${SRC}/privileged/csrc.sv "MTIME traps"] -item e 1 -fecexprrow 2 4
coverage exclude -scope /dut/core/priv/priv/csr/counters/counters/cntr[1] -linerange [GetLineNum ${SRC}/privileged/csrc.sv "assign NextHPMCOUNTERM"] -item b 1
# attempting to write stimecmp with STCE=0 traps, causing CSRSWriteM to go low
coverage exclude -scope /dut/core/priv/priv/csr/csrs/csrs -linerange [GetLineNum ${SRC}/privileged/csrs.sv "assign WriteSTIMECMPM"] -item e 1 -fecexprrow 5
# mode != m_mode and TVM = 1 causes a trap, causing CSRSWriteM to go low
coverage exclude -scope /dut/core/priv/priv/csr/csrs/csrs -linerange [GetLineNum ${SRC}/privileged/csrs.sv "assign WriteSATPM"] -item e 1 -fecexprrow 5 8
####################
# EBU
####################

12
tests/coverage/priv.S
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@ -298,6 +298,18 @@ sretdone:
wfi
///////////////////
// writing user level CSR in u mode
///////////////////
li a0, 3
ecall # enter machine mode
# set mstatus.FS to 01 to enable fp
li t0,0x4000
csrs mstatus, t0
li a0, 0
ecall # enter user mode
li t0, 5
csrw frm, t0
# Test uncovered privdec instructions