298 commits

Author	SHA1	Message	Date
Jordan Carlin	629cbf6cea	Gate more testbench volatile CSRs on supported extensions	2025-03-19 14:51:17 -07:00
Jordan Carlin	825d3ddc5f	Fix ccov	2025-03-11 22:51:14 -07:00
Jordan Carlin	3377dce425	Code coverage fixes	2025-03-11 13:59:52 -07:00
Jordan Carlin	d3a6a0e40f	A bit more cleanup	2025-02-13 01:46:15 -08:00
Jordan Carlin	36fb7992da	Rename coverage module	2025-02-09 23:23:33 -08:00
Jordan Carlin	8c102c6211	Move coverage tracer	2025-02-09 22:29:55 -08:00
Jordan Carlin	9ca2c935f8	Move RV_Assertions	2025-02-09 14:39:19 -08:00
Jordan Carlin	51986982a2	Merge branch 'main' of https://github.com/openhwgroup/cvw into fcov_lockstep	2025-02-08 21:24:21 -08:00
Jordan Carlin	2fe3686a24	More functional coverage refactoring	2025-02-07 16:50:37 -08:00
Huda-10xe	ed7b616c5b	Removing excess code	2025-02-07 00:13:27 -08:00
Huda-10xe	2db536bf49	Adding RISC-V Assertions	2025-02-06 23:47:43 -08:00
Jordan Carlin	ef8435ce88	Separate fcov and lockstep	2025-01-28 09:18:07 -08:00
Jordan Carlin	9fc2e23eee	Turn off debug mode	2025-01-25 17:35:37 -08:00
Jordan Carlin	a338089b6f	Fix FunctionName module naming	2025-01-25 16:22:27 -08:00
Jordan Carlin	8aabf57437	Add compressed instructions to name decoder	2025-01-13 09:13:45 -08:00
Jordan Carlin	7e021f9332	Only add Zfh to D conversion tests if D supported	2024-12-31 11:01:07 -08:00
Jordan Carlin	67843e647a	Mostly enable riscv-arch-test zcf and zcd tests ... Some tests disabled pending riscv-arch-test issue 590	2024-12-31 02:17:49 -08:00
Jordan Carlin	73e90847d9	Update Breker documentation	2024-12-19 14:09:42 -08:00
Jordan Carlin	d525cc25d8	Cleanup	2024-12-14 21:03:19 -08:00
Jordan Carlin	6cff03bd33	Breker tests working	2024-12-11 11:54:39 -08:00
Jordan Carlin	93813e8614	Merge branch 'main' of https://github.com/openhwgroup/cvw into breker	2024-12-08 20:57:18 -08:00
Jordan Carlin	783b81f8b8	VCD support in all simulators	2024-12-02 13:52:44 -08:00
Jordan Carlin	311125f4bd	WIP Breker	2024-12-02 13:11:55 -08:00
David Harris	05189d102a	Modifying tracer toward being able to run non-gc configurations in lockstep	2024-11-26 22:09:11 -08:00
David Harris	ce7b036b78	Merge pull request #1109 from jordancarlin/lint ... More lint cleanup: remove unused params	2024-11-16 16:34:15 -08:00
Jordan Carlin	00d02e5656	fix testbench	2024-11-16 12:53:10 -08:00
Jordan Carlin	2b57633217	Switch to out of tree riscv-arch-test with VM tests + add pmp & vm tests to testbench	2024-11-15 22:52:21 -08:00
Huda-10xe	b2789f304a	Removing old code (not in use anymore)	2024-11-15 00:39:16 -08:00
David Harris	0555e58afe	Removed unnecessary display statement from testbench for DTIM versions	2024-10-26 02:12:43 -07:00
Rose Thompson	083e583877	Added extra $display to print the test name during coverage.	2024-10-02 15:41:14 -05:00
Jordan Carlin	23f037e76e	Add misaligned cjal and cjalr tests	2024-09-29 22:33:11 -07:00
Jordan Carlin	330eda243c	Remove wally32i and wally64i tests since they are covered elsewhere now	2024-09-29 10:26:08 -07:00
Jordan Carlin	ef442808a9	Remove old imperas tests	2024-09-29 10:18:04 -07:00
David Harris	26f3c2a607	Added lockstep support for RV32. Not all wally privileged tests pass yet	2024-08-29 10:44:37 -07:00
David Harris	d4a8377406	Merge pull request #862 from jordancarlin/verilator_fixes ... Remove Verilator hack	2024-08-08 20:50:50 -07:00
David Harris	bc70f0b933	Merge pull request #869 from jordancarlin/installation ... Installation and setup overhaul	2024-08-08 15:39:23 -07:00
David Harris	fa98ae8c30	Depricate conditional generation based on A_SUPPORTED, which is now computed from ZALRSC_SUPPORTED and ZAAMO_SUPPORTED	2024-08-08 05:27:35 -07:00
Jordan Carlin	76eef03fe4	Merge branch 'main' of https://github.com/openhwgroup/cvw into installation	2024-08-07 20:22:55 -07:00
Huda-10xe	0303314f4e	Adding RVVI Functional Coverage Support	2024-08-07 14:31:16 +05:00
Jacob Pease	af2344d2d5	Merge branch 'main' of github.com:openhwgroup/cvw into spiboot	2024-08-06 17:09:39 -05:00
Jordan Carlin	42a9bbf28d	Merge branch 'main' of https://github.com/openhwgroup/cvw into installation	2024-07-25 21:21:57 -07:00
Jacob Pease	336a413f31	Added ability to split boot.memfile into boot.mem and data.mem.	2024-07-25 11:19:15 -05:00
Rose Thompson	d0a5b278b7	Factored out the rvvi testbench code into rvvitbwrapper.	2024-07-24 13:10:57 -05:00
Rose Thompson	b1a711ae0f	Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim.	2024-07-24 12:47:50 -05:00
Jordan Carlin	47452ddaaa	Remove hardcoded /opt/riscv	2024-07-23 23:29:45 -07:00
Rose Thompson	6c212ebf0e	Changes are confirmed to work on the FPGA.	2024-07-23 17:39:38 -05:00
Rose Thompson	7223b15134	Merge branch 'rvvi'	2024-07-22 12:01:01 -05:00
Rose Thompson	9471dcd296	Refactored the fpga and testbench so the RVVI can be synthesized cleanly and simulated without any major code changes. ... Adds three new configuration parameters to control enabling the RVVI packetizer and how much latency should exist between packets and the initial startup delay.	2024-07-19 17:08:47 -05:00
Rose Thompson	276cb558f0	Merge pull request #880 from davidharrishmc/dev ... wsim elf handling and RV64GCK lockstep support	2024-07-14 11:40:30 -05:00
David Harris	26d4fbcc19	Switched ImperasDV to RV64GCK model to support crypto (issue #872)	2024-07-13 21:42:14 -07:00