5 commits

Author	SHA1	Message	Date
Rose Thompson	8c99e28c8b	Fixed bugs in the fpga Makefile and vcu118 ddr memory gen script.	2024-09-03 21:03:38 -07:00
Rose Thompson	cde4598ed5	Updated vcu108 and vcu118 scripts to corrects set the clock speed.	2024-09-03 10:31:55 -07:00
Rose Thompson	d5e0382a81	vcu108 build now starts with make vcu108 and selects the correct ... memory size, starting address, device tree location, and clock speed for the zsbl and synthesis scripts.	2024-09-02 14:23:16 -07:00
Rose Thompson	2e55f1cecc	Well on the way to a fully automated FPGA build process which ... correctly sets the clocks and memory locations.	2024-09-02 11:19:02 -07:00
Rose Thompson	fc80bf1251	More updates to fpga IP module names.	2024-08-22 14:31:39 -07:00

Renamed from fpga/generator/xlnx_ddr4-vcu118.tcl (Browse further)