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11051 commits 7 branches 2 tags 58 MiB
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164 commits

Author SHA1 Message Date
David Harris
42f78c645b
Merge pull request #1363 from coreyqh/ccov 
Full privdec code coverage
 2025-04-15 12:33:16 -07:00
Corey Hickson
91e919395b CSRC full coverage 2025-04-15 11:07:55 -07:00
David Harris
521344b8b5 Fixed mstatus bits that should be read-only zero in certain configs (issue #1315) 2025-04-11 16:57:41 -07:00
David Harris
0528337a4a SUM and SPP are write only zeros if SATP and S are not supported 2025-04-11 16:21:05 -07:00
Corey Hickson
683c0cac86 Comment explaining redundant mstatus.FS check 2025-04-09 11:04:30 -07:00
Jordan Carlin
4b7be3e1ea
Fix mstatus.MPP write logic 2025-03-19 15:50:59 -07:00
David Harris
18e6e65a33 Clean up synthesis warnings about signed conversion 2025-03-05 09:49:21 -08:00
David Harris
c40450cc3a Fixed size bug and cleaned up PMP csr logic 2024-12-30 22:22:29 -08:00
David Harris
029f9e2d55 Fixed PMPCFG bits 6:5 need to be WARL 00 2024-12-30 19:16:59 -08:00
David Harris
155d1d511b Fixed funct7 code for sinval.vma (issue #1154) 2024-11-29 11:39:24 -08:00
Jordan Carlin
f6b0805fd4
More lint cleanup: remove unused params 2024-11-16 12:35:37 -08:00
Jordan Carlin
a462b9a2e6
Clean up verilator lint off commands and remove unnecessay ones 2024-11-15 23:52:50 -08:00
David Harris
150641e5d3 Implemented mhpmevent[3:31] as read-only zero rather than illegal 2024-10-15 09:08:25 -07:00
David Harris
de8a707361 Updated WARL field in senvcfg.CBIE to match ImperasDV 2024-10-14 15:28:56 -07:00
David Harris
43162aa088 Fixed handling writing reserved 10 value to mstatus.mpp 2024-10-14 08:42:52 -07:00
David Harris
5ef5633a62 Adjusted menvcfg.CBIE reserved 10 behavior to match ImperasDV; spec is ambiguous (riscv-isa-manual Issue #1682 2024-10-14 05:31:59 -07:00
David Harris
9ef211b40d mcountinhibit bit 1 should be hardwired to 0. Discovered during functional coverage testing 2024-10-13 20:59:01 -07:00
David Harris
e5d262063f Detect illegal writes to URO HPM counters 2024-08-15 10:43:20 -07:00
David Harris
125884eb74 Fixes mstatus.FS to also be set when a FP operation sets a floating-point flag even if it doesnt write a FP register 2024-08-13 07:34:58 -07:00
David Harris
faa1378920 Legalized PMPconfig WARL 2024-07-25 09:43:54 -07:00
David Harris
c4400dfeb0 Fixed WARL bug on MTVEC/STVEC alignment to 64 in vectored mode 2024-07-22 08:45:08 -07:00
Jordan Carlin
032de34dbd
Lint fixes for no priv mode configs 2024-06-26 22:15:18 -07:00
Jordan Carlin
c3cb4e5d1c
Fix FPU without S_SUPPORTED - #840 2024-06-26 22:00:29 -07:00
Ross Thompson
91c844ca45 Removed more *** from camline and csrc. 2024-06-19 12:31:50 -07:00
Ross Thompson
576f1b9e59 Moved the *** from trap to an issue. 2024-06-19 12:31:24 -07:00
Ross Thompson
ab1af0fabf Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2024-06-19 09:25:39 -07:00
David Harris
3fa37b0233 Lint cleanup 2024-06-18 06:15:17 -07:00
David Harris
53477b2c85 Code cleanup 2024-06-14 07:08:17 -07:00
David Harris
8f09240e6c Simplified outdated documentation pointers 2024-06-14 03:42:15 -07:00
Rose Thompson
04744032d8 Updated more signal names to match book. 2024-06-02 16:59:11 -05:00
Rose Thompson
b45b7ff7d6 Signal name changes to match book. 2024-06-02 16:32:25 -05:00
Jordan Carlin
4a72922087
update config to derive MISA from macros 
- Remove C_SUPPORTED and update decompress unit based on Zc* extensions
- Derive A_SUPPORTED from A subextensions
- Derive B_SUPPORTED from B subextensions
- Derive C_SUPPORTED from C subextensions
 2024-05-14 06:49:18 -07:00
David Harris
3f195884e9 Defined bit sizes more precisely to help VCS lint and conform to coding style 2024-04-21 08:40:11 -07:00
David Harris
3ea16c6057 Removed note about store stall being depricated 2024-04-17 03:34:11 -07:00
Kunlin Han
22b59138f0 Remove all #delay from non-testbench. 2024-03-16 11:20:32 -07:00
Kunlin Han
8c67a76912 Remove all #delay from non-testbench. 2024-03-13 10:31:40 -07:00
Rose Thompson
0d8c251fa4 Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-03-06 15:35:34 -06:00
David Harris
e0eb91f795 Changed always @(posedge clk) to always_ff @(posedge clk) where it was omitted in several places 2024-03-06 11:02:04 -08:00
David Harris
b386331cc8 Changed '0 to 0 where possible per Chapter 4 style guidelines 2024-03-06 05:48:17 -08:00
David Harris
dd33479056 Switched to ?: for gating per section 4.2.4.3 2024-03-06 04:59:58 -08:00
Rose Thompson
c093f53c9c Merge branch 'main' of https://github.com/openhwgroup/cvw 
Cleaned up the cacheLRU.
 2024-03-05 11:08:40 -06:00
David Harris
c77afcb7e6 Removed floprc with synchronous reset and synchornous clear 2024-02-19 22:28:55 -08:00
Rose Thompson
aa15a63d9c Merge branch 'main' of https://github.com/openhwgroup/cvw 2024-01-31 13:12:32 -06:00
David Harris
45e2317636 Added Wally github address to header comments 2024-01-29 05:38:11 -08:00
Rose Thompson
4c2ba2b0b4 Added StoreStall back to csrc. 2024-01-18 14:43:34 -06:00
David Harris
ed9fa07ba3 tests/coverage/tlbmisc.S 2024-01-15 07:16:11 -08:00
Rose Thompson
edc56c669e Fixed bug 546. non-leaf non-zero PBMT bit raise page fault. 2024-01-05 17:10:14 -06:00
David Harris
2c2f692f3a Moved forwarding logic into controller 2023-12-26 21:17:01 -08:00
David Harris
8eace30f49 Moved UnalignedPCNextF mux into IFU 2023-12-20 16:18:31 -08:00
David Harris
b0f34a6377 Made priority of misalignment depend on ZICCLSM_SUPPORTED and made StoreAmo take prioirty over load faults 2023-12-19 12:51:45 -08:00