Corey Hickson 91e919395b CSRC full coverage		2025-04-15 11:07:55 -07:00
..
cache	More lint cleanup: remove unused params	2024-11-16 12:35:37 -08:00
ebu	Updated email address authorship for my files.	2024-10-15 10:27:53 -05:00
fpu	exclude only impossible scenarios rather than whole line	2025-04-02 18:06:19 -07:00
generic	Clean up verilator lint off commands and remove unnecessay ones	2024-11-15 23:52:50 -08:00
hazard	Fixed FlushD exclusion	2025-04-03 10:16:54 -07:00
ieu	Fixed typos in controller	2025-02-26 09:58:47 -08:00
ifu	Decompressed and mmu coverage fixes	2025-04-11 06:42:20 -07:00
lsu	Full align code coverage	2025-04-08 01:51:22 -07:00
mdu	Clean up verilator lint off commands and remove unnecessay ones	2024-11-15 23:52:50 -08:00
mmu	Fixed cvw-arch-verif Issue #553 about misaligned lr/sc needs to throw access fault	2025-04-08 16:38:26 -07:00
privileged	CSRC full coverage	2025-04-15 11:07:55 -07:00
rvvi	Clean up or suppress synthesis warnings	2025-03-05 08:46:54 -08:00
uncore	Fixed clock edge for Design Compiler compatibility	2025-03-05 08:39:25 -08:00
wally	More lint cleanup: remove unused params	2024-11-16 12:35:37 -08:00
cvw.sv	Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim.	2024-07-24 12:47:50 -05:00