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36 commits
| Author | SHA1 | Message | Date | |
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Canberk Topal
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d659c96cda |
Update lowrisc_ip to lowRISC/opentitan@3a33c4df2
Update code from upstream repository https://github.com/lowRISC/opentitan to revision 3a33c4df2ed31b0d7a8936531a4ae9a275177f1b * [prim,rtl] Pass addr_i in no scrambling case (Canberk Topal) * [dvsim,xcelium] Avoid an OPTP2ND error if a plusarg isn't set (Rupert Swarbrick) * [dv,tcl] Merge Coverage Databases with union_all (Canberk Topal) * [prim_count] Add missing include (Pirmin Vogel) * [sram_ctrl] Additional write gating based on intg error (Michael Schaffner) * [sram_ctrl] Remove nonce reversal to improve timing (Michael Schaffner) * [sram_ctrl] Retime address mux to improve timing (Michael Schaffner) Signed-off-by: Canberk Topal <ctopal@lowrisc.org> |
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Canberk Topal
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4c1a4ed1df |
Update lowrisc_ip to lowRISC/opentitan@0747afbdd
Update code from upstream repository https://github.com/lowRISC/opentitan to revision 0747afbddec0ad176980429fe3100b32edb71d4a * [dv] Enable C/C++ code sourcing with VCS in .core (Canberk Topal) * [dv/dv_base_reg] Remove duplicated `get_map_by_name` method (Cindy Chen) * [prim] Pulse Sync assertion to check input/output (Eunchan Kim) * [sparse_fsm_flop] Create flop macro to increase DV coverage (Michael Schaffner) * [dvsim] Make build-randomization opt-in (Srikrishna Iyer) * [xcelium] Fix compile error (Srikrishna Iyer) * [dv/cov] fpv_csr_assert only collect assertion coverage (Cindy Chen) * [dv/jtag] Fix chip_level jtag csr rw failure (Cindy Chen) * [rtl] Convert some non-ANSI parameters to localparams (Rupert Swarbrick) * [prim] Waive unused parameters for Verilator in prim_generic_otp (Rupert Swarbrick) * [prim] Make a variable widening explicit in prim_present.sv (Rupert Swarbrick) * [prim] Waive some ALWCOMBORDER Verilator warnings in prim_arbiter_* (Rupert Swarbrick) * [prim] Fix Verilator lint warnings in prim_gf_mult.sv (Rupert Swarbrick) * [prim] Make some widening comparisons explicit in prim_clock_*.sv (Rupert Swarbrick) * [prim] Waive unused EnableAlertTriggerSVA for verilator lint (Rupert Swarbrick) * [bazel,dvsim] Add build rules for dvsim.py (Timothy Trippel) * [prim] Fix a bunch of Verilator lint errors in prim_packer.sv (Rupert Swarbrick) * [prim_sparse_fsm_flop/lint] Move waiver to correct file (Michael Schaffner) * [rv_dm dv] Test drive compile-time seed (Srikrishna Iyer) * [dvsim] Introduce Verilog compile-time seeds (Srikrishna Iyer) * [dvsim] Treat `tests: ["N/A"]` as an ignored testpoint (Srikrishna Iyer) * [hw/dv] Removed colon from Questa build and run fail patterns. (David Pudner) * [hw/dv] Code review changes for running questa simulations. (David Pudner) * [hw/dv] Added apache license header to questa_initial_setup.sh. (David Pudner) * [doc/ug] Updated opentitan documentation to include information about Questa use. (David Pudner) * [hw/dv] Added Questa dvsim files (David Pudner) * [dv/unr] Blackbox common security modules from UNR flow (Cindy Chen) * [dv] Minor fix to error message in mem_model.sv (Rupert Swarbrick) * [keymgr] Update keymgr to use prim_edn_req (Timothy Chen) * [doc] Fix rendering of special characters in testplan table (Rupert Swarbrick) * [dv] enable tlul_assert for csr part2 (Rasmus Madsen) * [dv] Enable tlul_assert for CSR tests (Weicai Yang) * [dv] Add valid/ready req/ack coverage for push_pull agent (Weicai Yang) * [dv,verilator] Make multiple sim_ctrl extensions play nicely (Rupert Swarbrick) * [chip dv] Add AST initialization routine (Srikrishna Iyer) * [top] auto generate (Timothy Chen) * [reggen] Make field 'qe' behavior consistent (Timothy Chen) * [prim] IFDEF_CODE waiver in sparsefsm flop (Eunchan Kim) * [dv] Update checklist for all blocks (Weicai Yang) * [dv/entropy_src] Temp remove stress_all_with_rand_reset test (Cindy Chen) Signed-off-by: Canberk Topal <ctopal@lowrisc.org> |
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Prajwala Puttappa
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c900ef1476 |
Update lowrisc_ip to lowRISC/opentitan@7c4f8b3fd
Update code from upstream repository https://github.com/lowRISC/opentitan to revision 7c4f8b3fde4bb625ac3330ff52d3f66507190fe5 Please note that we're adding push_pull_agent for the first time in this commit. Signed-off-by: Prajwala Puttappa <prajwalaputtappa@lowrisc.org> |
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Prajwala Puttappa
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15da12dfd6 |
Update lowrisc_ip to lowRISC/opentitan@7c4f8b3fd
Update code from upstream repository https://github.com/lowRISC/opentitan to revision 7c4f8b3fde4bb625ac3330ff52d3f66507190fe5 * Revert "[dv] Allow using memutil_dpi_scrambled even without prim_ram_1p_scr" (Rupert Swarbrick) * [dv] Fix some signed/unsigned comparison warnings (Rupert Swarbrick) * [dv] Make an implicit up-conversion explicit (Rupert Swarbrick) * [dv] Remove an unused array variable in prince_ref.h (Rupert Swarbrick) * [prim/security] Improve the code for prim_sparse_fsm security check (Cindy Chen) * [dv] Apply VCS option `-xprop=mmsopt` only when wave dump is off (Weicai Yang) * [all] variety of minor lint fixes (Timothy Chen) * [dv] Add options to improve VCS runtime (Weicai Yang) * [rv_dm] CSR test fixes (Srikrishna Iyer) * [dvsim] Fix pass/fail status for synthesis regression (Michael Schaffner) * [prim] Minor lint fixes for unused clocks / resets (Timothy Chen) * [dv] Flag illegal ENUMASSIGN warnings as errors (Michael Schaffner) * [flash_ctrl] Correct erase suspend interface behavior (Timothy Chen) * [rstmgr] Address several d2s review items (Timothy Chen) * [fpv/sec] Add some workaround logic for $cast keyword (Cindy Chen) * [dv] CSR seq lib - support for adapter-less RAL (Srikrishna Iyer) * [dv] Prepare codebase for UVM REG changes (Srikrishna Iyer) * [dv] Print computed CSR stuff in RAL (Srikrishna Iyer) * [dv] Allow CSR tests to run on custom RALs (Srikrishna Iyer) * [fpv/rom_ctrl] Check connectivity for alerts in rom_ctrl (Cindy Chen) * [prim] Add prim_and2 primitive (Pirmin Vogel) * [prim_dom_and_2share] Remove EnNegedge parameter (Pirmin Vogel) * [prim_dom_and_2share] Use prim_xor2 and prim_flop_en primitives (Pirmin Vogel) * [prim_dom_and_2share] Switch to single randomness input (Pirmin Vogel) * [util/dvsim] Fix confusing error message (Guillermo Maturana) * [dvsim] Minor changes to SynCfg results reporting (Michael Schaffner) * [fpv] V2S formal support (Cindy Chen) * [tools/xcelium] updated common coverage exclusions to exclude single bit correctly (Rasmus Madsen) * [dv] Clean up enable_reg_testplan (Weicai Yang) * [top] Hook-up flash/otp control and observation bus to ast (Timothy Chen) * [lint] Increase the unroll count (Eunchan Kim) * [entropy_src] Document & Implement THRESHOLD_SCOPE (Martin Lueker- Boden) * [AST] USB Observe, Clocks & POR_NI logic update (Jacob Levy) * [prim] Add new assertion macro for generating static lint errors (Pirmin Vogel) * [dv] csr_seq_lib fixes (Srikrishna Iyer) * [dv] dv_base_reg_block - Add special knobs (Srikrishna Iyer) * [dv] dv_base_mem - add special knobs (Srikrishna Iyer) * [prim] Move sec_cm assertion to an include file in prim_assert (Weicai Yang) * [flash_ctrl] Fixes for erase suspend (Timothy Chen) * [dv] exclude d_user.rsp_intg[6] for xcelium (Weicai Yang) * [prim_flop_en] Dependency fix (Michael Schaffner) * [dv] add mubi coverage for CSR and update reggen (Weicai Yang) * [prim] Add option for secure buffers in prim_mubi (Timothy Chen) * [prim] Add option for hand instantiated buffers for prim_flop_en (Timothy Chen) * [dv/shadow_reg] Move shadow_reg to V2S (Cindy Chen) * [prim_count] Updated comments to reflect all changes in lowRISC/opentitan#10378 (Michael Tempelmeier) * [dv] Teach ECC32 flavours of mem_area to write with integrity bits (Rupert Swarbrick) * [dv/shadow_reg] update milestone for shadow reg tests (Cindy Chen) * [checklists] Update V2S checklists (Srikrishna Iyer) * [tools/xcelium] updated xcelium flow to vcs for coverage test grading (Rasmus Madsen) * [prim] Add stub flops to remove lint warnings (Timothy Chen) * [dv] Add automatic covergroup for all regwen CSRs (Weicai Yang) * [dvsim] Add support for tags in testplan (Srikrishna Iyer) * [dv] Enable xcelium to include X for toggle coverage (Weicai Yang) * [dv] Clean up mem_bkdr_util__sram (Weicai Yang) * [util, testplan] Allow relative testplan imports (Srikrishna Iyer) * [prim] Add phase output to shadow register primitive (Pirmin Vogel) * [dv] Add assertion to check double_lfsr err triggers an alert (Weicai Yang) * [dv] Fix foundary failure (Weicai Yang) * [prim] update prim_count comment (Timothy Chen) * [prim_flop_2sync] Make the prim a standard non-generated prim (Michael Schaffner) * [dv/prim_max_tree] Fix xcelium compile error (Cindy Chen) * [dv] Fixes to enable foundry database pwrmgr_smoketest (Timothy Chen) * [dv] Add countermeasure verification for double_lfsr (Weicai Yang) * [dv] Update countermeasure verification (Weicai Yang) * [doc] Update V2S items (Weicai Yang) * [prim_max_tree] Remove dedicated FPV TB since all SVAs are embedded (Michael Schaffner) * [prim_max_tree/fpv] Add a simple formal testbench (Michael Schaffner) * [prim_max_tree] Create a primitive that calculates maxima (Michael Schaffner) * [dv] CSR / RAL model fixes (Srikrishna Iyer) * [uvmdvgen] bug fix (Srikrishna Iyer) * [dv] Fix some Xcelium warnings (Srikrishna Iyer) * [dv] Disable some benign warnings (Srikrishna Iyer) * [prim_mubi*_sender] Add option to omit sender flops (Michael Schaffner) * [dv, mem_bkdr_util] Fix ECC-computed backdoor WRs (Srikrishna Iyer) * [keymgr] sparsify the data control fsm (Timothy Chen) * [prim_lc_sender] Add AsyncOn parameter (Michael Schaffner) * [prim] Update behavior of prim_count (Timothy Chen) * [flash_ctrl] Minor fixes to flash foundry failure (Timothy Chen) * [sw,tests,pwrmgr] Improve synchronization (Guillermo Maturana) * [sw,tests] SRAM execution test DV integration (Dave Williams) * [dv] Update common_cov_excl to exclude d_user.rsp_intg[6] (Weicai Yang) * [otbn, dv] Added otbn_passthru_mem_tl_intg_err testcase (Prajwala Puttappa) * [rom_ctrl, dv] Fixes regression failures in rom_ctrl_passthru_mem_tl_intg_err (Prajwala Puttappa) * [dv/chip] Add jtag_csr_rw seq (Cindy Chen) * [chip dv] Remove xcelium build opt (Srikrishna Iyer) * [doc] Reorder D2S checklist items (Michael Schaffner) * [reggen] Add support for validation of RTL CM annotation (Michael Schaffner) * [all] various simple lint fixes (Timothy Chen) * [mem_bkdr,dv] Add missing type to otp_write_lc_partition_cnt (Rupert Swarbrick) * [dv/csr_utils_pkg] Clone ral map with top-level submaps (Cindy Chen) * [clkmgr] various spec and parameter updates (Timothy Chen) * [dv] Add ASSERT_NET to check net value (Weicai Yang) * [dv] revert lowRISC/opentitan#9050 and lowRISC/opentitan#9934 (Weicai Yang) * [primgen] Update AscentLint waiver in generated abstract prim wrappers (Pirmin Vogel) * [prim_generic] Fix lint errors (Pirmin Vogel) * [prim_count] Fix lint warnings (Pirmin Vogel) * [prim_alert_receiver] Fix ping during init sequence bug (Michael Schaffner) * [rom_ctrl, dv] Added passthru mem test (Prajwala Puttappa) * [prim_assert,dv] Use if condition in assert_init (Srikrishna Iyer) * [prim_filter_cnt] Make threshold runtime programmable (Michael Schaffner) * [prim_filter*] Optionally instantiate a 2-stage sync in prim_filter* (Michael Schaffner) * [dv] intg_err test cleanup and change passthru_mem_tl_intg_err to V2S (Weicai Yang) * [prim_xilinx] Replace KEEP with DONT_TOUCH attributes (Pirmin Vogel) * [sram/dv] Enable the integrity test for passthru (Weicai Yang) * [dv] Add integrity test for passthru mem (Weicai Yang) * [dv/tools] Fix alert ping exclusion (Cindy Chen) * [dv/mem_bkdr_util] added backdoor write of LC counter into LC partition in OTP (Dror Kabely) * [prim_pad_wrapper] Add dual pad wrapper for USB (Michael Schaffner) * [prim_clock_mux] Model generic mux with boolean ops (Michael Schaffner) * [prim_buf] Ensure generic primitives contain a logic cell (Michael Schaffner) * [prim_count] improved documentation and style (Michael Tempelmeier) * Revert "[dv] Replace fileset_partner flag with fileset_ast flag" (Michael Schaffner) * [dv] Replace fileset_partner flag with fileset_ast flag (Sharon Topaz) * [dv] Pass data_intg_passthru to dv_base_mem (Weicai Yang) * [dv/prim_alert] Add V3 item to testplan (Cindy Chen) * [dv/prim_count] Add an assertion to check max count stable (Cindy Chen) * [dv] Fix typo in uvmdvgen comment (Rupert Swarbrick) * [mem_bkdr_util] Use inverted integrity in rom_encrypt_write32_integ (Rupert Swarbrick) * [doc/checklist] Template fix (Cindy Chen) * [mem_bkdr_util,rom_ctrl] Fix how we call encrypt_sram_data (Rupert Swarbrick) * [rom/ram/xbar/otbn] Switch end-end bus integrity to inverted ECC codes (Michael Schaffner) * [dv/prim_alert_tb] Modify the seq to ensure alert always sends (Cindy Chen) * [dv,xcelium] Fix lowRISC/opentitan#4230: Xcelium compile error. (Timothy Trippel) * [dv/prim_alert] Add randomization in ping request sequence (Cindy Chen) * [prim_alert_receiver] Only check for ping requests after initialization (Michael Schaffner) * [doc] Update D2S checklist template and description (Michael Schaffner) * [prim_esc_receiver] Switch to standardized prim_count (Michael Schaffner) * [prim_count] Add option to disable the connection SVA (Michael Schaffner) * [otbn, rtl] Lint fixes (Greg Chadwick) * [sram/dv] Better support partial write in scb (Weicai Yang) * [dv/mem_bkdr_util] Fix ECC width error in OTP foundary test (Cindy Chen) * [secded/lint] Fix lint errors (Michael Schaffner) * [dv/prim_esc] Add more stimulus to reach coverage goal (Cindy Chen) * [alert_handler] Switch to sparse fsm primitive (Michael Schaffner) * [prim_sparse_fsm_flop] Add a parameter to disable SVA (Michael Schaffner) Signed-off-by: Prajwala Puttappa <prajwalaputtappa@lowrisc.org> |
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Michael Schaffner
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804c538db2 |
Update lowrisc_ip to lowRISC/opentitan@be1359d27
Update code from upstream repository https://github.com/lowRISC/opentitan to revision be1359d27d0e826e28e6611f318c286253cd05f1 * [secded_gen] Enhance inverted ECC code (Michael Schaffner) * [rtl] Add CRC32 primitive (Greg Chadwick) * [syn/cdc] Minor flow fixes in CDC and syn scripts (Michael Schaffner) * [dv] Minor update on mem_model (Weicai Yang) * [dv/prim_alert] Clean up alert test (Cindy Chen) * [bazel] Build verilator with bazel (Chris Frantz) * [cdc] Add support for initial CDC flow with open-source views (Michael Schaffner) * [lc_ctrl/dv,dv_lib,dv_utils,csr_utils] Added JTAG CSR Infrastructure (Nigel Scales) * [prim] Add a lint waiver for dv-only code / ifdefs (Timothy Chen) Signed-off-by: Michael Schaffner <msf@google.com> |
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Michael Schaffner
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4df2221dee |
Update lowrisc_ip to lowRISC/opentitan@34ba5e45f
Update code from upstream repository https://github.com/lowRISC/opentitan to revision 34ba5e45f9af7d8ca6c9bdae8bd11eeeeb669d6c * [dv] Add new ECC code options to mem_bkdr_util (Michael Schaffner) * [secded_gen] Define and generate inverted ECC enc/dec modules (Michael Schaffner) * [dv] Only run registers through one csr_rw sequence at once (Rupert Swarbrick) * [alert_handler] Minor lint fix (Michael Schaffner) * [prim_clock_div] Fix minor Verilator lint warning (Michael Schaffner) * [dvsim/lint] Make message reporting more flexible (Michael Schaffner) * [lint] Unify lint parser scripts (Michael Schaffner) * [rom_cntrl, dv] Test to verify successful rom check (Prajwala Puttappa) * [dv, dv_macros] Enhance `DV_GET_ENUM_PLUSARG` macro (Srikrishna Iyer) * [sram/dv] Fix mem data check (Weicai Yang) * [prim] Add flop wrapper for sparse fsm (Timothy Chen) * [flash_ctrl] Make data / metadata memories a single entry (Timothy Chen) * [dv] Teach encrypt/decrypt_sram_data to support OTBN (Rupert Swarbrick) Signed-off-by: Michael Schaffner <msf@google.com> |
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Canberk Topal
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53b1732b19 |
Update lowrisc_ip to lowRISC/opentitan@3a672eb36
This commit also adds memory manipulation package in ibex repository. Update code from upstream repository https://github.com/lowRISC/opentitan to revision 3a672eb36aee5942d0912a15d15055b1d21c33d6 * [mubi] Fix path in auto-gen header (Rupert Swarbrick) * [dv] Allow using memutil_dpi_scrambled even without prim_ram_1p_scr (Rupert Swarbrick) * [prim] Fix prim_ram_1p_scr Dependencies (Canberk Topal) * [dv/clk_rst_if] Split clk_rst_if jitter to 2 different values (Eitan Shapira) * [dv] Add external hjson path support in ralgen (Srikrishna Iyer) * [dv] Add sub RAL block creation knobs (Srikrishna Iyer) * [pwrmgr] Make rom_ctrl check signals multi-bit (Timothy Chen) * [dv/alert_handler] Randomize mubi input (Cindy Chen) * [flash_ctrl] Fix bank erase / info partition issue (Timothy Chen) * [ci] Fix CI failure (Weicai Yang) * [Cleanup] Remove lc_tx_e type and replace it with lc_tx_t (Weicai Yang) * [aes] Add gtech synthesis setup (Michael Schaffner) * [mubi] Enhance mubi_sync with stability check (Timothy Chen) * [prim] Fix prim_packer_fifo when ClearOnRead is false (Rupert Swarbrick) * [cleanup] Remove mubi4_e and replace it with mubi4_t (Weicai Yang) * [dv] Fix shape calculations for replicated ECC (Rupert Swarbrick) * [dv/alert] Support LPG in alert_sender/receiver pair (Cindy Chen) * [dv] Add a ReadWithIntegrity method to Ecc32MemArea (Rupert Swarbrick) * [dv] Simplify Ecc32MemArea read/write functions (Rupert Swarbrick) * [prim] Add option to not clear the packer FIFO upon read (Pirmin Vogel) * [dv] Change intg_err test from V3 to V2S (Weicai Yang) * [util] Delete generate_prim_mubi.py (Rupert Swarbrick) * [dv] Slightly generalise run_stress_all_with_rand_reset_vseq (Rupert Swarbrick) * [fpv] Fix some assumptions in prim_count (Cindy Chen) * [prim] quick path to prim_count assertion (Timothy Chen) * [dv] Support Multiple EDN Interfaces in OpenTitan (Canberk Topal) * [prim] Add xoshiro256pp primitive. (Vladimir Rozic) * [dv/prim_alert] Fix async fatal alert regression error (Cindy Chen) * [prim] Add missing include to prim_xilinx_pad_wrapper (Rupert Swarbrick) * [prim] Add missing include to prim_mubi_dec* (Rupert Swarbrick) * [dv/prim_alert_receiver] Fix assertion that consumes large mem (Cindy Chen) * [prim] Remove extra semicolon (Weicai Yang) * [chip,dv] Refactor CSR exclusion method (Srikrishna Iyer) * [top, all] update connects for mubi (Timothy Chen) * [flash_ctrl] Add plain text integrity in flash (Timothy Chen) * [prim] Add time-out functionality to prim_clock_meas (Timothy Chen) * [prim] Fix DC sythesis error (Weicai Yang) * [fpv] Fix regression failures (Cindy Chen) * [dv/ralgen] Update `dv_base_names` input from a string to a list (Cindy Chen) * [dv/ralgen] Update the `dv-base-prefix` optional input (Cindy Chen) * [doc] Add D2S and V2S checklist items to all checklists (Michael Schaffner) * [dv] Test security countermeasures (Weicai Yang) * [dv] Fix ASSERT_INIT race condition (Weicai Yang) * [syn/aes/otbn] Minor fixes to fix block level synthesis (Michael Schaffner) * [all] updated assert rtl ifdef (Timothy Chen) * [dv] Update TL intg testplan (Weicai Yang) * [prim] Add prim_fifo_async_sram_adapter to FPV list (Eunchan Kim) * [spi_device] Upload Cmd/Addr FIFO status revision (Eunchan Kim) * [dvsim] Modify resolve_branch to handle branch names with forward slash. (Todd Broch) * [prim_clock_inv] Add option to disable FPGA BUFG (Michael Schaffner) * [ralgen] Be more explicit which tool is called (Philipp Wagner) * [prim] Tweak prim_sync_reqack_data assertion so it can be disabled (Rupert Swarbrick) * [verible] Rename rule file (Philipp Wagner) * [dv/base_monitor] Cleaned up base monitor (Rasmus Madsen) * [fpv] prim_counter_fpv (Cindy Chen) * [dv/shadow_reg] Cross shadow reg error sequence with csr rw (Cindy Chen) * [dv] Fix scb multi-ral (Weicai Yang) * [dvsim] Enabling glob-style patterns for -i switch (Srikrishna Iyer) * [dv] Split sec_cm_testplan into multiple testplans (Weicai Yang) * [dv/dsim] Remove dsim's system_lib from library path (Guillermo Maturana) * [prim_packer] Resolve width mismatch (Philipp Wagner) * [prim] Fix lint error in prim_util_memload (Philipp Wagner) * [prim] Minor fix to make conn checks easy (Srikrishna Iyer) * [fpv] prim_secded FPV testbench updates bind file naming (Cindy Chen) * [dv_macros.svh] minor cleanup (Srikrishna Iyer) * [dv,xcelium] minor cleanup (Srikrishna Iyer) * [dv/shadowed_reset] Add a shadowed_rst_n interface (Cindy Chen) * [fpv] Update FPV file naming (Cindy Chen) * [top] Convert to mubi usage in some areas (Timothy Chen) * [entropy_src] mubi updates (Timothy Chen) * [prim] Add test for mubi invalid (Timothy Chen) * [prim_double_lfsr] Add duplicated LFSR primitive (Michael Schaffner) * [dv] Fix shadow reg backdoor path and enable csr_reset sequence (Weicai Yang) * [prim] Fix unused net (Timothy Chen) * [dv, clk_rst_if] Improve jitter and add scaling (Srikrishna Iyer) * [prim] Anchor buffers around register flip flops (Timothy Chen) * [alert_handler/top] Lint fixes and lc_tx_t to mubi4_t conversions (Michael Schaffner) * [prim_mubi] Replace true/false_value() functions with parameter (Michael Schaffner) * [dv/dsim] Get dsim to work at full chip (Guillermo Maturana) * [prim] Fixes for prim_count (Timothy Chen) * [top] Add various anchor points to modules (Timothy Chen) * [dv/pwrmgr] Add wakeup test sequence (Guillermo Maturana) * [reggen] Add mubi support into hjson (Timothy Chen) * [dv/shadow_reg] Fix aes shadow reg failure (Cindy Chen) * [dv/cdc] CDC simulation model (Udi Jonnalagadda) * [prim_lfsr/lint] Add temporary waiver for LOOP_VAR_OP lint error (Michael Schaffner) * [prim_clock_buf] Add lint waiver for unused parameter (Michael Schaffner) * [dvsim] Correctly set self_dir for included Hjson files (Philipp Wagner) * [util] Add tooling support for V2S milestone (Srikrishna Iyer) * [prim_mubi] Add decoder module similar to prim_lc_dec (Michael Schaffner) * [prim_mubi] Add mubi sender and sync primitives (Michael Schaffner) * [prim_mubi_pkg] Switch to True/False terminology (Michael Schaffner) * [prim] Minor work-around for xcelium (Timothy Chen) Signed-off-by: Canberk Topal <ctopal@lowrisc.org> |
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Rupert Swarbrick
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b66f199151 |
Update lowrisc_ip to lowRISC/opentitan@ad629e3e6
Update code from upstream repository https://github.com/lowRISC/opentitan to revision ad629e3e6e70c5eaa3c2dd68457b0a020448b35f * [dvsim] Introduce {self_dir} as variable (Philipp Wagner) * [dvsim] Small cleanups (Philipp Wagner) * [prim_lfsr] Minor lint fix (Michael Schaffner) * [dv] Update sec_cm testplan (Weicai Yang) * [prim/lint] Move waiver to correct waiver file (Michael Schaffner) * [prim_assert] Relocate waivers to dedicated prim_assert.waiver file (Michael Schaffner) * [alert_handler] Lint fixes and waiver updates (Michael Schaffner) * [prim_lc_receiver] Add parameter to select reset value (Michael Schaffner) * [lint] Add lint waiver for IP regfiles with shadow resets (Michael Schaffner) * [fpv] Fix Verible lint errors (Philipp Wagner) * [prim_lfsr] Minor lint fixes (Timothy Chen) * [clkmgr] Fix measurement control CDC (Timothy Chen) * [fpv/prim_counter] Pad one bit to include overflow case (Cindy Chen) * [fpv] Fix issue lowRISC#8371 (Zeeshan Rafique) * [flash_ctrl] Flash ctrl security hardening (Timothy Chen) * [dv] Fix CI error (Cindy Chen) * [prim_alert_*] Extend SVAs for FPV (Michael Schaffner) * [prim_alert_*] Update DV TB to respect initialization timing (Michael Schaffner) * [prim_alert_rxtx_fpv] Update FPV environment and fix SVAs (Michael Schaffner) * [prim_alert_sender] Update sender to support in-band reset mechanism (Michael Schaffner) * [prim_alert_sender] Simplify sender and clear ping req upon sigint (Michael Schaffner) * [prim_lc_sender] Add option to select reset value (Michael Schaffner) * [prim] Correct assertion valid term (Timothy Chen) * [prim_lc_combine] Align behavior of lc combine with mubi functions (Michael Schaffner) * [fpv/tool] Support GUI mode on dvsim (Cindy Chen) * [prim_lfsr] Further permutation refinements for SBox layer (Michael Schaffner) * [dv/shadow_reg] Shadow register write by field (Cindy Chen) * [prim] Fix the edge type (Eunchan Kim) * [checklist] Updates to checklist for D2 status (Tom Roberts) * [prim_mubi_pkg] Add a generic multibit type and associated functions (Michael Schaffner) * [prim] Minor fix and clarification to prim_count (Timothy Chen) * [keymgr/dv] Update testplan and covergroup plan (Weicai Yang) * [prim_lc_combine] Fix parameterization error (Michael Schaffner) * [fpv/prim_count] Small update on prim_count assertions (Cindy Chen) * [dv] Add ip_name in reg_block (Weicai Yang) * [keymgr] Finalize keymgr hardening (Timothy Chen) * [prim_lc_combine] Add a prim to compute logical AND/OR for LC signals (Michael Schaffner) * [dv] Remove common_cov_excl.el from unr.cfg (Weicai Yang) * [dv/top_level] Loop through the SW test multiple times (Cindy Chen) * [flash_ctrl] Various clean-up and updates (Timothy Chen) * [prim] Change prim_reg_cdc assertions (Timothy Chen) * [prim, keymgr] Migrate keymgr_cnt to prim_count (Timothy Chen) * [sw dv] Multi-site support for Verilator (Martin Lueker-Boden) * [dv/csr] Update write exclusion wdata value (Cindy Chen) * [dv/dv_base_reg] remove debug display (Cindy Chen) * [dv/shadow_reg] Fix alert shadow_reg regression error (Cindy Chen) * [top] Integrate ast into fpga (Timothy Chen) * [prim_lfsr] Improve statistics of non-linear output (Michael Schaffner) * [prim_esc_receiver] Fix response toggling corner case (Michael Schaffner) * option to use partner ast_pkg (Sharon Topaz) * [dv/prim_esc] Double the ping timeout cycles (Cindy Chen) * [dv] Use sed to add -elfile for each excl file (Weicai Yang) * [dv] Fix coverage report error (Weicai Yang) * [dv] Update common exclusion file (Weicai Yang) * [dv/prim_esc] Improve FSM coverage (Cindy Chen) * [reggen] Add a check to limit the swaccess type for shadow regs (Michael Schaffner) * [prim_subreg_shadow] Fix for W1S/W0C corner case (Michael Schaffner) * [prim_subreg_shadow] Disallow phase updates when storage err is present (Michael Schaffner) * [dvsim] Add passing count by milestone in reports (Srikrishna Iyer) * [dv/tool] Include toggle coverage for prim_alert_sender in cover_reg_top (Cindy Chen) * [clkmgr] Harden clock manager through frequency measurements (Timothy Chen) * [dv] Only enable VCS -kdb when dumping waves (Weicai Yang) * [dv] Fix shadow reg (Weicai Yang) * [dvsim] Allow non-integral values of --reseed-multiplier (Rupert Swarbrick) * [ast] Fixes for various ast issues (Timothy Chen) * [prim_esc_receiver] Assert escalation in case of sigint error (Michael Schaffner) * [prim_esc_receiver] Minor signal renaming for consistency (Michael Schaffner) * [dv/alert_handler] Support shadow register sequence (Cindy Chen) * [verilator] Use FileSz rather than MemSz when flattening ELF files (Michael Munday) * [prim_subreg_shadow] Only assert QE when committed_reg is written (Michael Schaffner) * [dv,verilator] Round up SV_MEM_WIDTH_BYTES to a multiple of 4 (Rupert Swarbrick) * [prim] Add missing include (Pirmin Vogel) * [dv/cover_cfg] Exclude prim_alert/esc from xcelium (Cindy Chen) * [dv/cover_cfg] Exclude prim_alert/esc pairs (Cindy Chen) * [clkmgr] Use local BUFHCE clock gates on FPGA (Pirmin Vogel) * [prim_prince] Mark "leaf" functions in prince_ref.h as static inline (Rupert Swarbrick) * [dv/shadow_reg] Check status after shadow_reg write (Cindy Chen) * [dv/shadwo_reg] Shadow reg common sequence update (Cindy Chen) * [otp_ctrl/lc_ctrl] Add 32bit OTP vendor test ctrl/status regs to LC TAP (Michael Schaffner) * [otp_ctrl] Add VENDOR_TEST partition (Michael Schaffner) * [prim] Edge Detector (Eunchan Kim) * [prim_diff_decode] Fix asynchronous assertions (Michael Schaffner) * [spi_device] Instantiate Upload module (Eunchan Kim) * [dv] Add sv_flist_gen_flags HJson var for FuseSoc (Srikrishna Iyer) * [dv, xcelium] Properly pass excl files to IMC (Srikrishna Iyer) * [reg] Fix shadow reg update during storage error (Timothy Chen) * [regfile] Refactor cdc handling to the reg level (Timothy Chen) * [dv/prim_esc] Add a testplan and increase coverage (Cindy Chen) * [dv] Update TLUL and EDN frequency (Weicai Yang) * [rstmgr, top] Add support for shadow resets (Timothy Chen) * [dv] Update Xcelium cover ccf (Srikrishna Iyer) * [dv] reduce seeds for CSR tests (Weicai Yang) * [usb/top] Remove AND gates on non-AON domain and rename 3.3V signal (Michael Schaffner) * [dv/prim_alert] Improvement on prim_alert tb (Cindy Chen) * [prim] FIFO SRAM Adapter fix (Eunchan Kim) * [prim] Add Write Mask port (Eunchan Kim) * [dv] Fix timescale issue with Xcelium (Weicai Yang) * [dv/prim_esc] Fix prim_esc regression error (Cindy Chen) * [dv/dv_base_reg] change from uvm_low to uvm_high (Cindy Chen) * [sram_ctrl] Harden initialization counter (Michael Schaffner) * [tools/uvmdvgen] Fix path in testplan inclusion (Guillermo Maturana) * [dv] Change stress_all_with_rand_reset to V3 (Weicai Yang) * [dv] fix tl error coverage (Weicai Yang) * [dv] Add macro DV_GET_ENUM_PLUSARG (Weicai Yang) * [prim] SRAM Async FIFO (Eunchan Kim) * [dv, xcelium] Fix statement coverage extraction (Srikrishna Iyer) * [dvsim] Minor fixes to coverage extraction (Srikrishna Iyer) * [prim_lfsr] Do not shadow |state| variable (Philipp Wagner) * [prim] Add non-linear out option to prim_lfsr (Timothy Chen) * [dv] Constrain TLUL to 24Mhz or higher (Weicai Yang) * [primgen] Instantiate tech libs in stable order (Philipp Wagner) * [primgen] Actually find the Verible Python wrapper (Philipp Wagner) * [dv/prim_esc] fix regression error (Cindy Chen) * [dv] Fix shadow reg predict (Weicai Yang) * [dv/common] Exclude assertion coverage from IP level testbench (Cindy Chen) * [dv/prince] hit additional toggle coverpoints (Udi Jonnalagadda) * [sram_ctrl] Update docs (Michael Schaffner) * [sram_ctrl] Absorb prim_ram_1p_scr (Michael Schaffner) * [dv/prim_alert/esc] Improvements for prim_alert/esc_tb (Cindy Chen) * [dv/dvsim] Add "testfile" grading option (Guillermo Maturana) * [dv/prim_esc] Direct test for prim_rx/tx (Cindy Chen) * [dv/utils] added 6MHz to clk_freq_mhz_e (Dror Kabely) * [prim_xor2/lint] Add waiver for .* use in generated prim (Michael Schaffner) * [dv, doc] Replace all 'dv.plan' with testplan (Srikrishna Iyer) * Fix the testplan link in dvsim code (Srikrishna Iyer) * [dv/dsim] Add dsim workaround for issue 242 (Guillermo Maturana) * [util, reggen] Support standardized cdc handling for regfile (Timothy Chen) * [dv/shadow_reg] Align shadow_reg field update behavior (Cindy Chen) * [dvsim] Fix publish report summary typo (Cindy Chen) * [rtl/prim_alert_sender] Allow ping_req to stay high without error (Cindy Chen) * [dvsim] Separate publish report from dvsim flow [PART3] (Cindy Chen) * [dv/prim_alert] Add a testbench for prim_alert (Cindy Chen) * [otp_ctrl] Connect test-related GPIO signal (Michael Schaffner) * [prim_subreg_shadow] Make local parameter a localparam (Philipp Wagner) * [prim_subreg] Make software access type an enum (Philipp Wagner) * [rtl/prim_diff_decode] Add prim_flop_2sync dependency (Cindy Chen) * [otp_ctrl] Update AscentLint waiver file (Michael Schaffner) * [edn] Add MaxLatency assertion (Eunchan Kim) * [prim_subreg_shadow] Correct write data signal usage (Michael Schaffner) * [script/dvsim] Separate publish report from dvsim flow [PART2] (Cindy Chen) * [prim_lfsr] Fix assertion issue occuring right after reset (Michael Schaffner) * [dv/shadow_reg] Handle CSR automated sequence write abort (Cindy Chen) * [dv/dv_lib] Add post_apply_reset for extra delay (Guillermo Maturana) * [dv] Add function coverage plan for tl_errors, tl_intg_err (Weicai Yang) * [dv] Remove tl_intg_err in top-level and increase seeds for tl_intg_err (Weicai Yang) * [dv/shadow_reg] Fix alert shadow reg regression error (Cindy Chen) Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org> |
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Philipp Wagner
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d003d479ff |
Update lowrisc_ip to lowRISC/opentitan@da3ac7c4e
Update code from upstream repository https://github.com/lowRISC/opentitan to revision da3ac7c4eb23a92194874ad2daf2e5f9e3330572 * [memutil] Allow use without scrambled memories (Philipp Wagner) * [prim_prince] Fix comment (Philipp Wagner) * [memutil] Fix width mismatch (Philipp Wagner) * [prim] Allow disabling SVAs ensuring REQ is held until ACK at run time (Pirmin Vogel) * [prim] Fix typo that caused fifo_async to get stuck (Timothy Chen) * [prim] Add a missing ROM_CFG_DEFAULT to prim_rom_pkg.sv (Rupert Swarbrick) * [dvsim] Do not assume the build failed if "ERROR" is printed (Philipp Wagner) * [prim_subreg_shadow] Invert meaning of SWACCESS in shadow/stage regs (Michael Schaffner) * [prim_arb_tree/rv_plic_target] Remove TODOs due to a Vivado tool bug (Michael Schaffner) * [primgen] Remove unused import (Philipp Wagner) * [primgen] Add shebang (Philipp Wagner) * [primgen] Make primgen "portable" again (Philipp Wagner) * [dv] Small optimization in memutil (Philipp Wagner) * [tools/ascent] updated ascent to use the --job-prefix option (Rasmus Madsen) * [otp_ctrl] Remove invalid command error (Michael Schaffner) * [tlul] Add some missing dependencies (Michael Schaffner) * [otbn/otp_ctrl] Replicate dmem scrambling keystream (Michael Schaffner) * [adc_ctrl] Various preparation steps for d2 (Timothy Chen) * [tools/dvsim] Fix some VCS flags (Guillermo Maturana) * Revert "[prim] Do remove prim_esc.core from the dependencies" (Rupert Swarbrick) * [prim] Remove dependency of prim:esc on a hardware block (Rupert Swarbrick) * [lint] prim_ram_1p_scr verilator lint fixes (Greg Chadwick) * [dv] Add scrambled_ecc32_mem_area for memutils (Greg Chadwick) * [dv] Add C++ memory scrambling model (Greg Chadwick) * [tools/dsim] Fix non-LRM compliant code (Guillermo Maturana) * [prim] Do remove prim_esc.core from the dependencies (Michael Schaffner) * [dv/dv_utils] Improvement on `max` function (Cindy Chen) * [alert_handler] Implement reverse ping feature (Michael Schaffner) * [prim_esc] Split the prims into their own core file (Michael Schaffner) * [dvsim] Fix GUI mode and launcher creation fixes (Srikrishna Iyer) * [dv/common] Stress_all_with_rand_reset apply reset concurrently (Cindy Chen) * [dv/all] update scoreboard `csr_addrs` accesses (Udi Jonnalagadda) * [dv/csr_utils] update unmapped_addr calculation (Udi Jonnalagadda) * [dv] Update intg alert names (Weicai Yang) * [dv, flash_ctrl] Fix the intr test (Srikrishna Iyer) * [prim_fifo_async] Fix a width calculation issue in case of Depth = 1 (Michael Schaffner) * [dv] Update VCS opt for uvm_hdl_* (Weicai Yang) * [dv, util] Make poll_for_stop() opt-in (Srikrishna Iyer) * [dvsim] Separate publish report option [PART1] (Cindy Chen) * [dv/kmac/sram] reduce iterations of smoke test (Udi Jonnalagadda) * [dv/stress_all_with_reset] Revert back IPs that uses apply_reset (Cindy Chen) * [dv/edn_reset] Fix apply_reset to concurrently deassert resets (Cindy Chen) * [dv] Update VCS cov merge opts (Srikrishna Iyer) * [dv] Add TL integrity error test for CSR (Weicai Yang) * [dv, chip] Remove USB clk driver (Srikrishna Iyer) * [script/dvsim] Update output folder (Cindy Chen) * [dv/edn_reset] Update IPs that overrides apply_reset task (Cindy Chen) * [dv/edn_reset] Fix stress_all_with_rand_reset error (Cindy Chen) * [dv/dv_base_scoreboard] remove duplicated code (Cindy Chen) * [otbn,dv] Teach otbn_memutil to track expected end address (Rupert Swarbrick) * [dv, dv_utils_pkg] Fix common int typedefs (Srikrishna Iyer) * [prim_lfsr] Fix spyglass lint warnings (Michael Schaffner) * [prim_clock_gating] Target 7series Xilinx devices (Philipp Wagner) * [dv/edn_rst] Add coverage to collect edn reset and dut reset (Cindy Chen) * [otp_ctrl/lc_ctrl] Add LC TAP register to control OTP test mechanisms (Michael Schaffner) * [prim_alert*/prim_esc*] Rework placement of size_only bufs/flops (Michael Schaffner) * [dv] fix a typo in tl_device_access_types_testplan (Weicai Yang) * [prim_otp] Rework generic model to match new error behavior (Michael Schaffner) * [dv/tlul_common_test] Add a testplan for TLUL integrity check (Cindy Chen) * [dvsim] Allow recursive testplan import (Srikrishna Iyer) * [primgen] Use verible-verilog-syntax for parsing (Mariusz Glebocki) * [prim] Break always_comb block to avoid apparent loop (Rupert Swarbrick) * [dvsim] Fix testplan bugs (Srikrishna Iyer) * [fpv] update secded_gen (Cindy Chen) * [dv/template] small fixes on index.md format (Cindy Chen) * [prim_otp] Add a waiver for power signal unused in generic prim (Michael Schaffner) * [simutil_verilator] Improve timeout handling (Rupert Swarbrick) * [testplans] Rename entries with testpoints (Srikrishna Iyer) * [dvsim/testplan] Fix the rendered testplan (Srikrishna Iyer) * [dv/cov] exclude prim_lfsr and prim_prince (Udi Jonnalagadda) Signed-off-by: Philipp Wagner <phw@lowrisc.org> |
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Rupert Swarbrick
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e0b477069e |
Update lowrisc_ip to lowRISC/opentitan@7117c349d
Update code from upstream repository https://github.com/lowRISC/opentitan to revision 7117c349d5465b5152d3bb774079013924a3e9ba * [dv/common] Improve coverage exclusion method (Cindy Chen) * [prim] Waive unused parameter warnings for an FPGA-specific param (Rupert Swarbrick) * [dpi] Fix indexing bug in ecc32_mem_area (Rupert Swarbrick) * [dv, xcelium] Dump covergroup report (Srikrishna Iyer) * [dvsim] Testplanner refactor & covergroup support (Srikrishna Iyer) * [otp_ctrl] Workaround for generated prim depending on generated prim (Michael Schaffner) * [dpi_memutil] Fix bug in RegisterMemoryArea (Rupert Swarbrick) * [rom_ctrl/dv] Add skeleton testbench (Tom Roberts) * [dvsim/verilator] Remove FUSESOC_IGNORE (Michael Schaffner) * [checklists] Update all checklists for consistency (Srikrishna Iyer) * [dv] Add integrity generation to backdoor memory loading (Greg Chadwick) * [prim_secded] Add C reference models for Hsiao encode (Greg Chadwick) * [rtl/prim_async_fifo] Fix async fifo typo when depth <= 2 (Cindy Chen) * [dv/unr] Fix unr clk rst ports (Cindy Chen) * [pads] - added AnalogIn1 pads for OTP supply (Arnon Sharlin) * [dv/common] add ECC support to mem_bkdr_if (Udi Jonnalagadda) Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org> |
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Philipp Wagner
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c7cb958f0d |
Update lowrisc_ip to lowRISC/opentitan@ca950b43a
Update code from upstream repository https://github.com/lowRISC/opentitan to revision ca950b43a0e9ef5013b8e2e5de765bc34fb59b74 Two updates to the Ibex code were required: * Adjust the prim_secded port names to match the changes in OpenTitan. * Replace `has_ral` in `ibex_icache_env_cfg.sv` and `ibex_icache_base_test.sv` with its newer equivalent, matching https://github.com/lowRISC/opentitan/pull/5932 and the additional updates in https://github.com/lowRISC/opentitan/pull/5951. Upstream changes include: * [prim_secded] Use _i/_o suffix for port names (Philipp Wagner) * [tl,dv] Allow bits to be set in responses regardless of mask (Rupert Swarbrick) * [push_pull agent] Driver code refactor (Srikrishna Iyer) * [dv/dvsim] Group failures per test in buckets (Guillermo Maturana) * [dv/uvmdvgen] Flag error for paths in block name (Guillermo Maturana) * [prim_fifo_async] Style fixes (Philipp Wagner) * Remove non-ASCII characters from SV code and meson.build (Rupert Swarbrick) * [dv/spi_device] Fix spi_device_csr_wr_with_rand_reset timeout issue (Cindy Chen) * [otp] Update to match latest foundry wrapper (Timothy Chen) * [flash] update to match latest foundry wrapper (Timothy Chen) * [top] Latest ast integration (Timothy Chen) * [lint] Strengthen Verible lint check to 100-character lines (Rupert Swarbrick) * [ prim ] Suppress unneeded assertion when clearing prim_packer_fifo (Martin Lueker-Boden) * [dv/otp_ctrl] Add coverage exclusions (Cindy Chen) * [dv/dvsim] Add "^Error:" as a run fail pattern. (Guillermo Maturana) * [dvsim] Fix column bug in DV summary report (Srikrishna Iyer) * [dvsim] Fix testplan test counts (Srikrishna Iyer) * [dvsim] Fix lowRISC/opentitan#6061 (Srikrishna Iyer) * [prim_clock_div] Update waiver (Michael Schaffner) * [fpv] dvsim script error (Cindy Chen) * [prim_otp] Update interface (Michael Schaffner) * [dvsim] update edacloudlauncher imports (Udi Jonnalagadda) * [dv/doc] Minor fix on dv_doc (Cindy Chen) * [dvsim] Scheduler updates - max_parallel, max_poll (Srikrishna Iyer) * [dvsim] Set `Deploy.job_name` more robustly (Srikrishna Iyer) * [prim] Make SECDED prim generation deterministic (Rupert Swarbrick) * [tool, xcel] Support dumpping the array of struct in shm/vcd (Tung Hoang) * [dv/otp_ctrl] OTP_CTRL DV doc (Cindy Chen) * [dv/dv_macros] Fix DV_PRINT_ARR_CONTENTS (Guillermo Maturana) * [prim_pad_attr/prim_flop_en] Add waiver files (Michael Schaffner) * [prim_usb_diff] Minor lint fix (Michael Schaffner) * [prim_clock_div] Update waiver file (Michael Schaffner) * [top] change prim_generic usage into prim (Timothy Chen) * [formal/conn] Support dvsim to publish regression result summary (Cindy Chen) * Add formatting changes from allow list (Rafal Kapuscik) * [prim] Add generic and Xilinx-specific xor2 primitives (Pirmin Vogel) * [prim] Add Width parameter to buffer primitives (Pirmin Vogel) * [prim] Add generic and Xilinx-specific enable-FF primitives (Pirmin Vogel) * [prim] Remove temporary workaround in parameter list related to primgen (Pirmin Vogel) * [dv/dvsim] Provides more context on some failures. (Guillermo Maturana) * [dvsim] Fix local run error. (Eunchan Kim) * [dv] Support multi-ral (part 4) (Weicai Yang) * [dv/dvsim] Adds failure bucketizer for triage. (Guillermo Maturana) * [lint/docs] Update ascentlint dvsim command in readme (Michael Schaffner) * [top] Various top level lint fixes (Timothy Chen) * [pinmux/padring] Wire up the pad attribute WARL behavior modules (Michael Schaffner) * [dv] Fix tl_error failure (Weicai Yang) * [pinout] Update flash test mode and voltage signals/pads (Michael Schaffner) * [pad_wrapper] Extend the generic and Xilinx pad wrapper models (Michael Schaffner) * [dv] Update scb for all blocks (Weicai Yang) * [dv] Support multi-ral (part 3) (Weicai Yang) * [prim_arbiter,lint] Tell Verilator to split variables for scheduling (Rupert Swarbrick) * [prim] Fix lint warnings, replace inline AscentLint waivers (Pirmin Vogel) * [dvsim] Scratch root default to $REPO_TOP/scratch (Srikrishna Iyer) * [dv] Update `process_tl_access` args for all blocks (Weicai Yang) * [dv] Support multi-ral (part 2) (Weicai Yang) * [formal] Clean up some formal warnings (Cindy Chen) * [topgen] Rework pinmux datastructure and templatize tops (Michael Schaffner) * [otp_ctrl] Several small lint fixes (Michael Schaffner) * [prim_fifo_async] Make async FIFO output zero when empty (Noah Moroze) * [flash] Improve flash ECC handling based on transasction attribute (Timothy Chen) * [dv] Remove toggle coverage excl for a_user/d_user (Weicai Yang) * [dvsim] Fix remaining comments from lowRISC/opentitan#5876 (Srikrishna Iyer) * [dv] Support multi-ral (part 1) (Weicai Yang) Signed-off-by: Philipp Wagner <phw@lowrisc.org> |
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Rupert Swarbrick
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7d61def943 |
Update lowrisc_ip to lowRISC/opentitan@f29a0f7a7
Update code from upstream repository https://github.com/lowRISC/opentitan to revision f29a0f7a7115e03fba734b1c00691c253aceb07e. The list of OpenTitan changes that are merged in appears at the bottom of the commit. There are some manual changes needed to adapt the code to work with these changes. - The ICache monitors need some extra types to adapt to the (rather odd) data model that the OpenTitan dv_lib code now uses, where a monitor needs to know an agent's associated sequence type. - Verilator simulations now use MemArea slightly differently OpenTitan changes: * [dv] Allow monitor items to have different types from sequence items (Rupert Swarbrick) * [dvsim] Fix primary_cfg handling (Srikrishna Iyer) * [dvsim] Deal with non unicode chars in log files (Srikrishna Iyer) * [dvsim] Added common build fail patterns (Srikrishna Iyer) * [dvsim] Minot cleanup to the lint flow (Srikrishna Iyer) * [dvsim] Minor cleanups to to formal flow (Srikrishna Iyer) * [dvsim] Fixes to UNR and cov analysis flows (Srikrishna Iyer) * [dvsim] Very minor cleanup of Deploy class (Srikrishna Iyer) * [dvsim] LsfLauncher report early errors as F (Srikrishna Iyer) * [dvsim] Minor fix in clean_odirs function (Srikrishna Iyer) * [chip dv] Set +sw_images as comma-separated list (Srikrishna Iyer) * [flash_ctrl] Split tl intefaces for flash_ctrl and prim_flash_cfg (Timothy Chen) * [keymgr] Fix input value checks (Timothy Chen) * [formal/script] Update generic formal flow naming from `fpv` to `formal` (Cindy Chen) * [top, prim] Address wmask and data width mismatch issue (Timothy Chen) * [dvsim] Add GUI mode for running simulations (Srikrishna Iyer) * [dv] Fix reg backdoor (Weicai Yang) * [dpi] Make an "ECC32" flavour of MemArea (Rupert Swarbrick) * [uvmdvgen] Fix has_interrupts in env_cfg (Cindy Chen) * [dvsim] Keep dependencies list (Srikrishna Iyer) * [prim_prince] Reverse the k0||k1 mapping to match with the paper (Michael Schaffner) * [dvsim] Fix printing of last 10 lines (Srikrishna Iyer) * [primgen] Minor fix to enable types with underscores (Michael Schaffner) * [dvsim] Prevent command echo suppression (Srikrishna Iyer) * [dvsim] Spot fixes for LSF and internal launcher (Srikrishna Iyer) * [sva] csr assertion dependency update (Cindy Chen) * [memutil] Change DpiMemUtil so that it no longer owns MemAreas (Rupert Swarbrick) * [memutil] Factor out MemArea as a class (Rupert Swarbrick) * [prim] Split out PRESENT and PRINCE support from prim:all (Rupert Swarbrick) * [fpv/otp_ctrl] Disable assertions due to lc_esc_en (Cindy Chen) * [prim_prince] Annotate some arrays to avoid UNOPTFLAT warnings (Rupert Swarbrick) * [top] Hook up latest ast ports and complete a few other integration (Timothy Chen) * Eliminate `#pragma once` in favor of include guards (Chris Frantz) * [sw,dv] Update headers to pass fix_include_guards.py (Alex Bradbury) * [xbar/dv] Fix assertion error due to short reset (Weicai Yang) * [sram] Add memory initialization (Timothy Chen) * [uvmdvgen] Update links in checklist template (Philipp Wagner) * [dv/uvmdvgen] Add comment for testplan (Cindy Chen) * [dv/top_earlgrey] chip csr_aliasing timeout (Cindy Chen) * [dvsim] Cosmetic updates to launcher methods (Srikrishna Iyer) * [dv] Update csr_wr to support field write (Weicai Yang) * [dv/common] Fix regression warnings (Cindy Chen) * [dv] Get blocks with multiple device interfaces working with chip DV (Rupert Swarbrick) * [doc] Use relative links in Hjson-related shortcodes (Philipp Wagner) * [dvsim] minor enhancement to clean_odir (Srikrishna Iyer) * [dvsim] Statically display jobs' status (Srikrishna Iyer) * [dvsim] Do weighted scheduling of jobs (Srikrishna Iyer) * [dvsim] Schedule jobs by dependency (Srikrishna Iyer) * [dv] Xcelium UNR typo (Srikrishna Iyer) * [dvsim] Implement LsfLauncher (Srikrishna Iyer) * [dv/chip] solve same_csr_outstanding_timeout (Cindy Chen) * [dv] make dv_base_agent work for high-level agent (Weicai Yang) * [tools/dv] added UNR flow for xcelium (Rasmus Madsen) * [prim] Split prim:subreg out of prim:all (Rupert Swarbrick) * [prim] Split prim_alert_* out of prim:all (Rupert Swarbrick) * [prim] Split out fifos into a prim_fifo core (Rupert Swarbrick) * [prim] Split out arbiters into a prim_arbiter core (Rupert Swarbrick) * [prim] Make prim:flop_2sync depend on prim:flop (Rupert Swarbrick) Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org> |
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Tom Roberts
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2c75c2b2ec |
Update lowrisc_ip to lowRISC/opentitan@1ae03937f
Update code from upstream repository https://github.com/lowRISC/opentitan to revision 1ae03937f0bb4b146bb6e736bccb4821bfda556b * [prim/fifo_async] Add assertions on pointers (Tom Roberts) * [prim/fifo_async] Add support for Depth <= 2 (Tom Roberts) * [prim/fifo_async] Code tidy-up (Tom Roberts) * [top / ast] Continued ast integration (Timothy Chen) * [dvsim] Use bash when running make underneath (Srikrishna Iyer) * [prim] Increase maximum width for prim_util_memload to 312 (Greg Chadwick) * [sram_ctrl] Fix potential back-to-back partial write bug (Michael Schaffner) * [dvsim] Fix for lowRISC/opentitan#5527 (Srikrishna Iyer) * [lint] Waive Verilator UNUSED warnings for packages (Rupert Swarbrick) * [uvmdvgen] Update DV doc path and terminology (Srikrishna Iyer) * [clkmgr] Fix dft issues (Timothy Chen) * [util] add `dec` types to prim_secded_pkg (Udi Jonnalagadda) * [util] minor updates to secded_gen (Udi Jonnalagadda) * [lint] Fix a bunch of lint warnings related to long lines (>100 chars) (Michael Schaffner) * [dv] Update common intr_test seq (Weicai Yang) * [util] Slight refactor of secded_gen.py (Timothy Chen) * [tlul] Add memory transmission integrity checks (Timothy Chen) * [dvsim] Move clean_odirs to `util.py` (Srikrishna Iyer) * [dvsim] Split Deploy into Deploy and Launcher (Srikrishna Iyer) * [dvsim] Add utils.TS_FORMAT* vars (Srikrishna Iyer) * [dv/lock_reg] Update IPs to adopt the lock_reg changes (Cindy Chen) * [dv/enable_regs] Support enable registers have more than one field (Cindy Chen) * [dv/base_reg] use m_field instead of accessing field (Cindy Chen) * [dv/sram] add SRAM scrambling model for DV (Udi Jonnalagadda) * [dv/tools] Updated Coverage flow for xcelium (Rasmus Madsen) Signed-off-by: Tom Roberts <tomroberts@lowrisc.org> |
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Tom Roberts
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5ef18f0b78 |
Update lowrisc_ip to lowRISC/opentitan@6cc5c164b
NOTE this commit includes various changes to align the Ibex repo with changes upstream in OT! Update code from upstream repository https://github.com/lowRISC/opentitan to revision 6cc5c164ba96d339f06cbcede0d17d2c96ce3c05 * [dv] Add SV_FCOV_SVA back (Srikrishna Iyer) * [DV][FCOV] Minor updates to lowRISC/opentitan#5414 (Srikrishna Iyer) * [dvsim] Fix --cov + --build|run-only bugs (Srikrishna Iyer) * [lint] Waivers for rv_core_ibex lint (Greg Chadwick) * [lint] Allow one branch in unique case (Greg Chadwick) * [dv/macros] Add fcov macros from Ibex (Tom Roberts) * [dvsim/verilator] Fix pre-build cmd failure when hw/foundry is absent (Michael Schaffner) * [verilator/otp] Enable OTP preloading in verilator (Michael Schaffner) * [dvsim] Use builtins wherever possible (Srikrishna Iyer) * [prim] Avoid an apparent combinatorial loop in prim_secded_*_dec.sv (Rupert Swarbrick) * [dv/shadow_reg] Fix aes shadow reg error (Cindy Chen) * [lint] Remove comportable waivers from non-comportable IPs (Michael Schaffner) * [dv] Fix VPD dumping (Srikrishna Iyer) * [prim] Waive Verilator lint warning in prim_lfsr.sv (Pirmin Vogel) * [dv] Hard code various dv connections until full hook-up (Timothy Chen) * [tlul] Add payload checker and generator on device side only. (Timothy Chen) * [prim_packer] Silence verilator width warnings (Rupert Swarbrick) * [dvsim] lint fixes to FlowCfg (Srikrishna Iyer) * [dvsim] Minor improvement to FlowCfg (Srikrishna Iyer) * [dvsim] lint fixes to Scheduler (Srikrishna Iyer) * [dvsim] Very small update to Timer. (Srikrishna Iyer) * [lint] Update Verible lint parser to detect Verible syntax errors (Michael Schaffner) * [lint] Spot errors in the lint flow that we weren't expecting (Rupert Swarbrick) * [lint] Remove Fusesoc-related message waivers (Michael Schaffner) * [top / rst] Adjust the way rst_ni is used in design (Timothy Chen) * [dvsim/syn] Update parsing script and area reporting (Michael Schaffner) * [dv/regwen] update REGWEN conventions (Cindy Chen) * [dv/tools] Bug fix to common.tcl tb_top section. (Eitan Shapira) * [dv] Fix stress_all with reset (Weicai Yang) * [prim] Add a new slow to fast clock synchronizer (Tom Roberts) * [prim] Minor lint fix (Tom Roberts) * [tlul] Add instruction type to tlul (Timothy Chen) * [top] Ast updates (Timothy Chen) * [lint] Increase threshold for max number of bits in an array (Michael Schaffner) * [dv] add dv_base_reg_pkg to env_pkg template (Udi Jonnalagadda) * [dv/verilator] Ignore foundry dir (Srikrishna Iyer) * [dv] Provide license diagnostic info for VCS (Srikrishna Iyer) * [prim/otp_ctrl] Fix ECC correctable bug in generic OTP wrapper (Michael Schaffner) * [prim_ram_1p_scr] Make parity and diffusion layer settings more flexible (Michael Schaffner) * [prim] fix flash sram adapter use for configuration space (Timothy Chen) * [dv] Make CSR fields randomizable by default. (Srikrishna Iyer) * [dv/prim] minor updates (Udi Jonnalagadda) * [top] Minor lint fixes (Timothy Chen) * [prim_flash] Flash port alignments (Michael Schaffner) * [prim_util_pkg] Fix DC warning in _clog2() (Philipp Wagner) * Add missing full_o output signal of prim_fifo_sync (Philipp Wagner) * [dv] Gracefully kill simulation (Srikrishna Iyer) * [dv] Minor updates to prim tbs (Srikrishna Iyer) * [flash / top] Minor edits based on reviews (Timothy Chen) * [flash_ctrl / top] Various functional updates to flash (Timothy Chen) * [dv/otp_ctrl] regwen sequence (Cindy Chen) * [prim] Wire up full_o sync fifo output port in prim_sram_arbiter (Rupert Swarbrick) * [dvsim] Generate FUSESOC_IGNORE at top of scratch root (Rupert Swarbrick) * Revert "[lint] Remove Fusesoc-related message waivers" (Michael Schaffner) * Revert "[lint] Rename tool warnings to flow warnings and reduce their severity" (Michael Schaffner) * Revert "[lint] Provision syntax error filter for Verible lint" (Michael Schaffner) * [prim] Update fifo behavior during reset (Timothy Chen) * [dv] Move cip related macros to cip_macros (Weicai Yang) * [dv/dvsim] Fix when next_item does not have dependency (Cindy Chen) * [prim_packer_fifo/rtl] reset to disable output controls (Mark Branstad) * [lint] Provision syntax error filter for Verible lint (Michael Schaffner) * [lint] Rename tool warnings to flow warnings and reduce their severity (Michael Schaffner) * [lint] Remove Fusesoc-related message waivers (Michael Schaffner) * [dv/dvsim] collect coverage in scheduler (Cindy Chen) * [dvsim] Fix Syn class (Michael Schaffner) * [dv/shadow_reg] move get_shadow_regs function to dv_base_ral_block (Cindy Chen) * [lc_ctrl] Switch ECC to standard Hamming code (Michael Schaffner) * [prim_ram_*p_adv/prim_otp] Add option to use standard Hamming ECC (Michael Schaffner) * [secded_gen] Fix template bug that results in lint error (Michael Schaffner) * [prim/fifo_async] Disallow non-power-of-two depths (Tom Roberts) * [dv/alert] update shadow_reg alert naming in DV (Cindy Chen) * [dv] Align csr::reset_asserted to actual reset pin (Weicai Yang) * [prim_secded*_fpv] Generate FPV testbenches (Michael Schaffner) * [prim_secded*] Regenerate all SECDED primitives (Michael Schaffner) * [secded_gen] Add ability to generate FPV TB's and correct Hamming code (Michael Schaffner) * [dvsim] Run cov_merge / cov_report as part of the main set of jobs (Rupert Swarbrick) * [dvsim] Get rid of Deploy's static dispatch_counter (Rupert Swarbrick) * [dvsim] Make the scheduling logic per-target (Rupert Swarbrick) * [dvsim] Remove "status" from Deploy items (Rupert Swarbrick) * [dvsim] Create jobs with dependencies instead of sub-jobs (Rupert Swarbrick) * [dvsim] Simplify SimCfg._gen_results (Rupert Swarbrick) * [dvsim] Factor deploy method out of Deploy object (Rupert Swarbrick) * [dvsim] Move time tracking into its own class in Deploy.py (Rupert Swarbrick) * [dvsim] Fix printing of Deploy objects (Rupert Swarbrick) * [dv] make dv_macros.svh more UVM_agnostic (Srikrishna Iyer) * [dv/prim] reduce smoke test iterations (Udi Jonnalagadda) * [dv/hmac] reduce runtime for sha_vector test in smoke regression (Cindy Chen) * [DV] Enable cov comp creation iff cov is enabled (Srikrishna Iyer) * [prim_alert] Fix xcelium compile error (Cindy Chen) * [alert_rxtx/fpv] Update alert sender FPV testbenches (Michael Schaffner) * [alert_rxtx] Add option to latch fatal alert in alert sender (Michael Schaffner) * [kmac/dv] KMAC smoke test (Udi Jonnalagadda) * [dv/str_utils_pkg] add byte_to_str function (Udi Jonnalagadda) * [prim] - Add new prim_lc_dec (Jacob Levy) * [util] Move design-related helper scripts to util/design (Michael Schaffner) * [prim-flash] Add missing deps (Srikrishna Iyer) * [dv] Define SIMULATION during DV sims (Michael Schaffner) * [dv] Fix a typo in tb.sv.tpl (Weicai Yang) * Cleanup: Remove executable bits from source files (Philipp Wagner) * [dv] Use separate clock for EDN (Weicai Yang) * [dv] Add macro DV_EDN_IF_CONNECT to simplify EDN connect in TB (Weicai Yang) * [dv] Fix typo in clk_rst_if (Weicai Yang) Signed-off-by: Tom Roberts <tomroberts@lowrisc.org> |
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Greg Chadwick
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d717e2385e |
Update lowrisc_ip to lowRISC/opentitan@7aa5c2b89
Update code from upstream repository https://github.com/lowRISC/opentitan to revision 7aa5c2b890fa5d4e3d0b43e0f5e561cb7743a01d * [flash] updated flash wrapper md file (Dana Agur) * [flash / top / ast] functional updates (Timothy Chen) * [ralgen, dv] Associated changes to ralgen (Srikrishna Iyer) * [prim_sync_reqack_data] Fix SVA checking DST-to-SRC data stability (Pirmin Vogel) * [dv/keymgr] temp disable alert checking in scb (Cindy Chen) * [dvsim] Fix a wrong path in print message (Weicai Yang) * [prim] Teach verilator to recognise a clock gate (Rupert Swarbrick) * [prim_lc_sync] Add AsyncOn parameter to enable/disable the sync flops (Michael Schaffner) * [clkmgr / top] Add clock divider step down to support lc_ctrl transition (Timothy Chen) * [prim_sync_reqack] Use NRZ protocol internally for increased throughput (Pirmin Vogel) * [prim] correct interface documentation. (Timothy Chen) * [flash_ctrl] Add tlul configuration interface to prim_flash (Timothy Chen) * [flash_ctrl] Use hamming code for 64b ECC (Timothy Chen) * [prim/edn] Fix lint error (width mismatch) (Eunchan Kim) Signed-off-by: Greg Chadwick <gac@lowrisc.org> |
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Philipp Wagner
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b1daf9e44e |
Update lowrisc_ip to lowRISC/opentitan@c277e3a8
Update code from upstream repository https://github.com/lowRISC/opentitan to revision 7e131447da6d5f3044666a17974e15df44f0328b Updates to Ibex code to match this import: * Include str_utils in the imported code. * List new source files in dv/uvm/core_ibex/ibex_dv.f * Update patches to resolve merge conflicts. * Update tb_cs_registers.cc and ibex_riscv_compliance.cc to match the new return code of simctrl.Exec(). Imported updates: * Do not require pyyaml >= 5.1 (Philipp Wagner) * [prim_edn_req] Forward fips signal to consumer (Pirmin Vogel) * [prim_edn_req] Use prim_sync_reqack_data primitive (Pirmin Vogel) * [prim_edn_req] De-assert EDN request if packer FIFO has data available (Pirmin Vogel) * [cleanup] Mass replace tabs with spaces (Srikrishna Iyer) * [lc_ctrl] Add script to generate the LC state based on the ECC poly (Michael Schaffner) * [dvsim] Use list for rsync command (Eunchan Kim) * [verilator] Only control the reset line when necessary (Rupert Swarbrick) * [dv/csr_utils] Add debug msg for UVM_NOT_OK err (Cindy Chen) * [dvsim] Add exclude hidden files when needed (Eunchan Kim) * [prim_sync_reqack] Add variant with associated data and optional data reg (Pirmin Vogel) * [DV, Xcelium] Fix for lowRISC/opentitan#4690 (Srikrishna Iyer) * [dvsim] Remote copy update (Srikrishna Iyer) * [prim_edn_req] Add EDN sync and packer gadget primitive (Michael Schaffner) * [prim] Add hamming code as ECC option (Timothy Chen) * [DV] Cleanup lint warnings with Verible lint (¨Srikrishna) * [prim_ram] Rearrange parity bit packing and fix wrong wmask settings (Michael Schaffner) * [lc_sync/lc_sender] Absorb flops within lc_sender (Michael Schaffner) * [prim_otp_pkg] Move prim interface constants into separate package (Michael Schaffner) * [sram_ctrl] Pull scr macro out of sram_ctrl (Michael Schaffner) * [top] Move alert handler to periphs and attach escalation clock to ibex (Michael Schaffner) * [prim_esc_rxtx/rv_core_ibex] Add default values and NMI synchronization (Michael Schaffner) * [dvsim] Fix regression publish result link with --remote switch (Cindy Chen) * [vendor/ibex] Remove duplicate check tool requirements files (Michael Schaffner) * [prim_ram_1p_scr] Fix sequencing bug in scrambling logic (Michael Schaffner) * [prim_ram*_adv] Qualify error output signals with rvalid (Michael Schaffner) * [dvsim] Fix purge not delete remote repo_top (Cindy Chen) * [lc/otp/alerts] Place size-only buffers on all multibit signals (Michael Schaffner) * [prim_buf] Add generic and Xilinx buffer primitive (Michael Schaffner) * [prim] Packer to add byte hint assertion (Eunchan Kim) * [dvsim] Logic to copy repo to scratch area (Srikrishna Iyer) * [dv/lc_ctrl] enable lc_ctrl alert_test (Cindy Chen) * [prim] documentation update for flash (Timothy Chen) * [flash_ctrl] Add additional interface support (Timothy Chen) * [dvsim] Fix publish report path (Weicai Yang) * [top_earlgrey] Instantiate LC controller in toplevel (Michael Schaffner) * [doc] Fix checklist items in V1 (Michael Schaffner) * [dv/csr_excl] Fix VCS warning (Cindy Chen) * [dv/doc] cleaned up checkist alignment (Rasmus Madsen) * [doc/dv] cleanup (Rasmus Madsen) * [dv/doc] updated dv_plan links to new location (Rasmus Madsen) * [dv/doc] changed testplan to dv_plan in markdown files (Rasmus Madsen) * [dv/doc] changed dv plan to dv doc (Rasmus Madsen) * Remove redundant ascentlint options (Olof Kindgren) * Add ascentlint default options for all cores depending on lint:common (Olof Kindgren) * [flash] documentation update (Timothy Chen) * [flash / top] Add info_sel to flash interface (Timothy Chen) * [otp] lci interface assertion related fix (Cindy Chen) * [dv/uvmdvgen] Add switch to auto-gen edn (Cindy Chen) * [util] Rejig how we load hjson configurations for dvsim.py (Rupert Swarbrick) * added changes required by sriyerg (Dawid Zimonczyk) * update riviera.hjson (Dawid Zimonczyk) * [flash_ctrl] Add high endurance region attribute (Timothy Chen) * Change VerilatorSimCtrl::Exec to handle --help properly (Rupert Swarbrick) * Simplify handling of exit_app in VerilatorSimCtrl::ParseCommandArgs (Rupert Swarbrick) * [sram_ctrl] Rtl lint fix (Michael Schaffner) * [keymgr] Add edn support (Timothy Chen) * [dv] Make width conversion explicit in dv_base_env_cfg::initialize (Rupert Swarbrick) * [dvsim] Allow dvsim.py to be run under Make (Rupert Swarbrick) * [dvsim[ rename revision_string to revision (Srikrishna Iyer) * [dvsim] Update log messages (Srikrishna Iyer) * [dvsim] fix for full verbosity (Srikrishna Iyer) * [dv] Fix Questa warning and remove unused var (Weicai Yang) * [dvsim] Add alias for --run-only (Weicai Yang) * [keymgr] Hook-up random compile time constants (Timothy Chen) * [dvsim] Add support for UVM_FULL over cmd line (Srikrishna Iyer) * [dv common] Enable DV macros in non-UVM components (Srikrishna Iyer) * [DVsim] Add support for Verilator (Srikrishna Iyer) * [DVSim] Fix how sw_images is treated (Srikrishna Iyer) * [DV common] Fixes in sim.mk for Verilator (Srikrishna Iyer) * [DV Common] Split DV test status reporting logic (Srikrishna Iyer) * [prim_arbiter_ppc] Fix lint error (Philipp Wagner) * [DV common] Factor `sim_tops` out of build_opts (Srikrishna Iyer) * [dvsim] run yapf to fix style (Weicai Yang) * [dv/common] VCS UNR flow (Weicai Yang) * [dv] Add get_max_offset function in dv_base_reg_block (Weicai Yang) * [otp_ctrl] Fix warnings from VCS (Cindy Chen) * [lint] Change unused_ waiver (Eunchan Kim) * [dv/alert_test] Add alert_test IP level automation test (Cindy Chen) * [DV] Update the was SW is built for DV (Srikrishna Iyer) * [dvsim] Replace `sw_test` with `sw_images` (Srikrishna Iyer) * [chip dv] Move sw build directory (Srikrishna Iyer) * [dv common] Update dv_utils to use str_utils_pkg (Srikrishna Iyer) * [DVSim] Method to add pre/post build/run steps (Srikrishna Iyer) Signed-off-by: Philipp Wagner <phw@lowrisc.org> |
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Rupert Swarbrick
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4852e307b7 |
Update lowrisc_ip to lowRISC/opentitan@e619fc60
This updates the vendored code from OpenTitan and fixes up patches as we go. The biggest change is that the support files that were in dv/data have moved to dv/tools/dvsim (with a couple of other internal renames). The icache test code also needs the corresponding path change and to rename its regression from "sanity" to "smoke" (the new name for the default regression). Update code from upstream repository https://github.com/lowRISC/opentitan to revision e619fc60c6b9c755043eba65a41dc47815612834 * [dv] Remove duplicated keys from common_sim_cfg.hjson (Rupert Swarbrick) * [dv] two small fix in dv (Cindy Chen) * [dv] Comment out example build modes from common_sim_cfg.hjson (Rupert Swarbrick) * [dv/keymgr] Cleanup some warnings in xcelium (Weicai Yang) * [lc_ctrl] Reuse an instance of the RISC-V dmi_jtag as the LC TAP (Michael Schaffner) * [otp_ctrl] Update LC types within OTP (Michael Schaffner) * [lc_ctrl] Add first cut implementation (Michael Schaffner) * [flash_ctrl] update prim flash interface (Timothy Chen) * [flash_ctrl] Add support for isolated flash partition (Timothy Chen) * [dv/common] update naming from sanity to smoke (Cindy Chen) * [prim] update naming from sanity to smoke (Cindy Chen) * [dv/base] add get_reg_by_name support in dv_base_reg_block (Cindy Chen) * [cov methodology] Functional coverage prototype (Srikrishna Iyer) * [dv] Fix tpyo (Weicai Yang) * [dv common] Wave dumping improvements / fix (Srikrishna Iyer) * [dv] Fix for `--run-only` switch (Srikrishna Iyer) * [prim_present] Add support for iterative full-round PRESENT (Michael Schaffner) * [dv] Fix VCS compile error (Weicai Yang) * [sparse-fsm-encode] Switch to Safe Rust Encoding (Sam Elliott) * [sparse-fsm-encode] Disallow Complementary Encodings (Sam Elliott) * [prim/util] Fix parameter type when using prefixes (Pirmin Vogel) * [keymgr/prim_lfsr] Correct minor errors in core files (Michael Schaffner) * [design checklist] avoid using word sanity (Cindy Chen) * [prim_lc_sync] Add two stage sync for life cycle control signals (Michael Schaffner) * [flash] update flash program to support ack / done / last (Timothy Chen) * [prim] update prim flash to have ack / done support (Timothy Chen) * Fix typo in testplan template (Rupert Swarbrick) * [dv] Fix license header for some cfg files (Weicai Yang) * [dv] Only check scoreboard from pre_abort if we were in run phase (Rupert Swarbrick) * [doc] Add lint requirements to V1 checklist (Cindy Chen) * [dv common] Minor enhancements to dv_reg_block (Srikrishna Iyer) * [dv] Fix library paths for dsim (Srikrishna Iyer) * [keymgr/dv] Update testbench (Weicai Yang) * [dv/common] Add DV_ALERT_IF_CONNECT macro (Weicai Yang) * [dv, common] Promote VCS warning to error (Srikrishna Iyer) * [prim] update clock_mux prim to avoid using BUFG (Timothy Chen) * [clkmgr] Add divider bypass during test mode (Timothy Chen) * [opt_ctrl] Change state_q assignment to ease debugging (Michael Schaffner) * [doc] Update D2 checklist and propagate updates to IPs (Michael Schaffner) * [dv/dvsim] Fix -c option compile error (Cindy Chen) * [dv] Tidy up use of get_normalized_addr (Rupert Swarbrick) * [fpv] Fix fusesoc dependecy issue (Cindy Chen) * [lint] Fix lint warning (Cindy Chen) * [dv/lint] Add new DV TB to lint batch script (Cindy Chen) * [fpv] Add lint checking to FPV tb (Cindy Chen) * [dvsim] Remove process_exports() from the code (Srikrishna Iyer) * [dvsim] Fix HJson bugs (Srikrishna Iyer) * [fpv] alert_rx/tx updates (Cindy Chen) * [prim] slicer lint fix (Eunchan Kim) * [prim] Packer to remove unused parameter. (Eunchan Kim) * [prim_lfsr] Update prim_lfsr and testbench to use correct perm width (Michael Schaffner) * [prim_lfsr] Add script to generate seed and perm constants (Michael Schaffner) * [dv/common] Upgrade some VCS warnings to errors (Weicai Yang) * [dvsim] Document and slightly improve subst_wildcards in utils.py (Rupert Swarbrick) * [csrng/dv] Initial dv environment (Steve Nelson) * [sparse-fsm-encode] Update template to prevent JG compile error (Michael Schaffner) * Gracefully shut down Verilator when software test fails (Philipp Wagner) * [otp] fix FPV compile error (Cindy Chen) * [dvsim] Kill subprocesses more gracefully (Rupert Swarbrick) * [prim] Fix Verilator lint warnings (Pirmin Vogel) * [memutil] Allocate the right number of bytes in StagedMem::GetFlat() (Rupert Swarbrick) * [memutil] Load ELF files via a staging area (Rupert Swarbrick) * [memutil] Add iterator and merging insertion interfaces to RangedMap (Rupert Swarbrick) * [memutil] Factor out "ranged map" implementation from dpi_memutil (Rupert Swarbrick) * [alert_handler] update alert hander ports (Timothy Chen) * [otp_ctrl] Update OTP output data mapping (Michael Schaffner) * [otp_ctrl] Split partition metadata into separate package (Michael Schaffner) * [prim_otp] Add TL-UL regfile for testing (sim only) (Michael Schaffner) * [memutil] Split out the non-verilator part of verilator_memutil (Rupert Swarbrick) * [dv/common] Update DV_CHECK_* macros (Weicai Yang) * [dv/common] Fix testplan path (Weicai Yang) * [prim_assert] Fixed non-UVM part of `ASSERT_ERROR (Srikrishna Iyer) * [otp_ctrl] Simplify and consolidate OTP error codes (Michael Schaffner) * [kmac] Fix critical syntax errors. (Eunchan Kim) * [dv/common] Move testplan from tools directory to data (Weicai Yang) * [dvsim] Rename verbosity wildcards to something more informative (Rupert Swarbrick) * [dv/lfsr] Update prim_lfsr_sim_cfg.hjson and add coverage (Udi Jonnalagadda) * [dv common] Added string check macros (Srikrishna Iyer) * [rtl] Use platform-agnostic log macros prim_assert (Srikrishna Iyer) * [dv] Minor fixups to dv_Utils_pkg (Srikrishna Iyer) * [dv] Fix platform-agnostic log macros (Srikrishna Iyer) * [checklist] Upgrade wording for D1 milestone (Scott Johnson) * [entropy_src/rtl] fix for dv sanity test (Mark Branstad) * [lint] Add option to bail out on first invalid Tcl cmd (Michael Schaffner) * [sram_ctrl] Add first cut implementation (Michael Schaffner) * [prim] Fix AscentLint waiver that made the tool crash (Michael Schaffner) * [checklists] Clean up and align HW and SW checklists (Michael Schaffner) * [prim] Update signal name in lint waiver rule (Pirmin Vogel) * [flash_ctrl] Switch to new keyschedule in PRINCE (Michael Schaffner) * [lint] fix the waiver format (Eunchan Kim) * [dv] Waive lint warnings in dv_macros.svh (Srikrishna Iyer) * [dv common] Add platform-agnostic log macros (Srikrishna Iyer) * [util] Add Rust Enum Support to sparse-fsm-encode.py (Sam Elliott) * [util] Add C Enum Support to sparse-fsm-encode.py (Sam Elliott) * [sparse-fsm-encode] Expand error and help messages (Michael Schaffner) * [dv/common] TLUL agent function coverage (Weicai Yang) * [dv/shadow_reg] support alert handshake checking (Cindy Chen) * [prim_present/otp_ctrl] Add round index state IOs to primitive (Michael Schaffner) * [dv] Fix 2 regression failures (Weicai Yang) * [prim_multibit_sync] Add multibit synchronizer with consistency check (Michael Schaffner) * [prim] Fix Lint warning for prim_slicer (Eunchan Kim) * [prim_generic_otp] Add TL-UL test interface stub for DV (Michael Schaffner) * [doc] Improve documentation for common_ifs (Rupert Swarbrick) * [doc] Improve pins_if block diagram (Rupert Swarbrick) * [prim_prince/present] Remove TODOs (Michael Schaffner) * [dv/common] Change TL item content when it's not accepted (Weicai Yang) * [dv/uvmgen] update has_alerts (Cindy Chen) * [dv/common] Add run opt plusarg to enable file path in the log (Weicai Yang) * [prim] Add clock buffer primitive for Xilinx FPGAs (Pirmin Vogel) * [otp_ctrl] Provision power sequencing signals (Michael Schaffner) * [dv/common] Clean up old makefile flow (Weicai Yang) * [entropy_src/rtl] review round2 changes (Mark Branstad) * [otp_ctrl] Update all FSMs to use prim_flop for the state (Michael Schaffner) * [prim_xilinx_flop] Add a Xilinx version with keep attribute (Michael Schaffner) * [prim/util] Update sparse-fsm-encode and include FSM template (Michael Schaffner) * [DV macros] minor enhancement to `DV_SPINWAIT (Srikrishna Iyer) * [DV common] Add DV_ASSERT_CTRL macro (Srikrishna Iyer) * [DV common] Enhance `DV_CHECK_MEMBER_RANDOMIZE_*` (Srikrishna Iyer) * [otbn] Use relative scope names for OTBN scopes (Rupert Swarbrick) * [verilator simutil] Add support for relative scope names to SVScoped (Rupert Swarbrick) * [fpv/prim_packer] remove assumption (Cindy Chen) * [fpv/csr_assert] support all modules for CSR assert (Cindy Chen) * [memutil] Teach verilator_memutil to load multi-segment ELF files (Rupert Swarbrick) * [memutil] Simplify how we read ELF files in verilator_memutil.cc (Rupert Swarbrick) * [memutil] Add a "verbose" flag to detail memory loads (Rupert Swarbrick) * [memutil] Parse all arguments before loading anything (Rupert Swarbrick) * [memutil] Use override keyword, not virtual for overridden method (Rupert Swarbrick) * [memutil] Use exceptions to simplify error handling (Rupert Swarbrick) * [memutil] Store the width of memory areas in bytes, not bits (Rupert Swarbrick) * [memutil] Allow memory locations to have associated LMAs (Rupert Swarbrick) * [memutil] Improve type of ElfFileToBinary in verilator_memutil.cc (Rupert Swarbrick) * [verilator simutil] Move SVScoped class into dv/verilator/cpp (Rupert Swarbrick) * [memutil] Move static functions out of VerilatorMemUtil class (Rupert Swarbrick) * [memutil] Run clang-format on verilator_memutil.* (Rupert Swarbrick) * [dv:entropy_src] Initial rng_agent and integrated into entropy_src env (Steve Nelson) * [prim_ram_adv/fpv] fix assertion (Cindy Chen) * [prim_ram_1p_scr] Simplify nonce input and align to multiples of 64b (Michael Schaffner) * [fpv/csr_assert] add csr support for regwen (Cindy Chen) * [prim*] Various lint fixes in the prims (Michael Schaffner) * [prim] remove FPV related assertions (Eunchan Kim) * [prim_lfsr] Add option to supply custom output permutation (Michael Schaffner) * [dv/common] calculate addr map size in RAL (Weicai Yang) * [flash_ctrl] Add ECC to program / erase datapaths (Timothy Chen) * [otp_ctrl] First cut implementation of the OTP controller (Michael Schaffner) * Fix invalid read in verilator_memutil (Rupert Swarbrick) * [doc] Don't strip markdown headings from HW checklist (Philipp Wagner) * [site] Set lint title (Tobias Wölfel) * [dv/prim] add basic PRINCE testbench (Udi Jonnalagadda) * [flash_ctrl] Support the notion of a 'program-repair'. (Timothy Chen) * [prim/tlul] Various small lint fixes (Michael Schaffner) * [dv/uvmdvgen] update dvsim and remove Makefile (Cindy Chen) * [util] Add script for generating sparse FSM encodings (Michael Schaffner) * [prim] Add option to register output for interrupts (Timothy Chen) * [prim_otp] First cut implementation of FPGA emulation (Michael Schaffner) * [prim_ram_1p_adv] Add 16bit ECC mode (Michael Schaffner) * [chip dv] Fix for failing GPIO test (Srikrishna Iyer) * [RTl] Generic pad wrapper default behavior fix (Srikrishna Iyer) * [slicer] Select partial from bitstream (Eunchan Kim) * [util] Don't hack __repr__ in FlowCfg (Rupert Swarbrick) * [util] Fix lint in dvsim.py (Rupert Swarbrick) * [fpv/prim_packer] Add a FPV TB (Cindy Chen) * [Keccak] Keccak_f implementation (Eunchan Kim) * [dv/csr] add common task for csr_or_field_rd_check (Cindy Chen) * [keccak] Add valid signal to random value (Eunchan Kim) * [prim] Add primitive clock divider (Timothy Chen) * [dv/shadow_reg] update sequence for storage error (Cindy Chen) * [dv/lib] clear csr_outstanding_access after reset (Cindy Chen) * [sw] Ensure Headers are Correctly Ordered (Sam Elliott) * [dv] Fix csr_rd check during reset (Weicai Yang) * Adding the first update to coverage methodology (Rasmus Madsen) * [dv] TL agent supports no clock reset (Weicai Yang) * [tlul/dv] Update test plan for tl errors (Weicai Yang) * [fpv/alert] update namings for FPV tb (Cindy Chen) * [keccak] Masked/Unmasked Keccak single round (Eunchan Kim) * [lint/prim*] Waive STAR_PORT_CONN_USE errors in generated prims (Michael Schaffner) * [prim_usb_diff_rx] Carry over wrapper for USB diff receiver (Michael Schaffner) Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org> |
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Rupert Swarbrick
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623402cf6f |
Vendor in hw/dv/{data,tools} from OpenTitan
This gets the rest of the support code needed for dvsim (which we currently duplicate). The patch: - adds the relevant directories to the vendoring file - adds a patch to rewrite some OpenTitan-specific bits - adds a "common_project_cfg.hjson" - re-runs the vendoring tool This patch won't yet change how DV code runs; we also need to redirect a couple of paths and delete dv/uvm/data for that. This will happen in the next patch. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org> |
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Rupert Swarbrick
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690f8af65e |
Update paths for vendored DV code
This commit amends some paths in the vendoring hjson file (and updates config files to use things at the new paths). Finally it re-runs the vendoring tool: Update code from upstream repository https://github.com/lowRISC/opentitan to revision 92e9242424c72c59008e267dd3779e2af5ec8e83 which just ends up with a load of file renames. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org> |
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Rupert Swarbrick
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d71aaeee06 |
Update lowrisc_ip to lowRISC/opentitan@92e92424
The shortlog from the vendor tool's automated patch is reproduced at
the bottom of this commit message.
The automated commit is squashed with one to update how we depend on
bus parameters. Before, we had to provide an "Ibex top package". This
behaved the same as OpenTitan's "lowrisc:constants:top_pkg", but
avoided having to vendor in that file.
On the OpenTitan side, this has been tidied up with commit
d266c68 ("[dv] Update dv_utils sources to use bus_params_pkg"). This
changes the dependency of dv_utils to
"lowrisc:opentitan:bus_params_pkg". We still have to provide our
own (now called "lowrisc:ibex:bus_params_pkg") and need to patch the
dv_utils dependency, but this is a bit cleaner because dv_utils is
less likely to accidentally include dependencies on OpenTitan
internals.
On our side, we have to update the vendoring patch for dv_utils (and
change its name). We also need an equivalent patch for dv_lib. Then we
rename our hacky "Ibex top package" to "bus_params_pkg". The ICache DV
environment also needs patching to use the bus parameters properly.
Phew!
* [dv] Update prim_present cov opt (Srikrishna Iyer)
* [dv] Align VCS and Xcelium cov var names (Srikrishna Iyer)
* [dv] Split coverage for functional and auto tests (Srikrishna Iyer)
* [dvsim] Do builds smartly (Srikrishna Iyer)
* [syn] Carry over synthesis flow updates from bronze (Michael
Schaffner)
* [dvsim] Lint cleanup (Srikrishna Iyer)
* [dvsim] Allow testplan to be omitted (Srikrishna Iyer)
* [dvsim] Address lowRISC/opentitan#3071 comments (Srikrishna Iyer)
* [dvsim] lint cleanup (Srikrishna Iyer)
* [dvsim] Add support for second-level indirection (Srikrishna Iyer)
* [dvsim] Change cores-root to avoid conflicts with autogen'd core
files (Michael Schaffner)
* [dvsim] Update `tests` key behavior in regressions (Srikrishna Iyer)
* [lint] Minor update of ERROR patterns in parser script (Michael
Schaffner)
* [packer] Revise the implementation (Eunchan Kim)
* [flow] Remove lint makefile (Timothy Chen)
* [flows] Various updates to tools and documents to suppose top/ip
select (Timothy Chen)
* [dv/shadow_reg] shadow_reg update error (Cindy Chen)
* [rtl/alert] change the naming from _en_i to _req_i (Cindy Chen)
* [dvsim] Tidy up config file loading in FlowCfg.py (Rupert Swarbrick)
* [dvsim] Make it simpler to derive from FlowCfg (Rupert Swarbrick)
* [lint] Update warning/error exclusions in parser scripts (Michael
Schaffner)
* [dvsim] Fix for `--tool` override (Srikrishna Iyer)
* [dvsim] Bug fix in LintCfg.py (Srikrishna Iyer)
* [prim/dv] Integrate LFSR TB with dvsim (Udi Jonnalagadda)
* [uvmdvgen] Update template to reflect bind reorg (Srikrishna Iyer)
* [dv] remove prim_lfsr_bind (Srikrishna Iyer)
* [dv] Cleanup lint warnings in csr_utils_pkg (Srikrishna Iyer)
* [dv] Cleanup lint warnings in clk_rst_if (Srikrishna Iyer)
* [dvsim] Fix coverage dashboard link (Srikrishna Iyer)
* [prim] Rename prim_util_memload.sv to svh (Philipp Wagner)
* [lint/doc] Update linting readme to reflect recent updates (Michael
Schaffner)
* [lint] Remove legacy Makefile flow for linting tools (Michael
Schaffner)
* [dvsim/lint] Enable Verilator lint in Dvsim (Michael Schaffner)
* [prim_arbiter_fixed/fpv] Add generated FPV testbench (Michael
Schaffner)
* [prim_arbiter_fixed] This adds a fixed priority arbiter (Michael
Schaffner)
* [prim] Domain-Oriented Masking AND logic (Eunchan Kim)
* [dv] Update dv_utils sources to use bus_params_pkg (Srikrishna Iyer)
* [dv] Update mem_model to use bus-params_pkg (Srikrishna Iyer)
* [dv] Update dv_lib sources to use bus_params_pkg (Srikrishna Iyer)
* [uvmdvgen] Support for setting vendor name in VLNV (Srikrishna Iyer)
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Rupert Swarbrick
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46ff63ad88 |
Properly vendor in mem_model from OpenTitan
This removes the manually copied version at dv/uvm/core_ibex/common and vendors things properly now that the vendor tool supports such things (this picks up the same OpenTitan version as the previous commit: lowRISC/opentitan@067272a2). |
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Rupert Swarbrick
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e37c81a1c1 |
Update lowrisc_ip to lowRISC/opentitan@067272a2
Update code from upstream repository https://github.com/lowRISC/opentitan to revision 067272a253f4eeed4ae58a9171ee266256528117 * [dv/common] initial support for shadow register (Cindy Chen) * [rtl/prince] Small fixes for PRINCE cipher logic (Udi Jonnalagadda) * [dv doc] Fix rendered testplan table (Srikrishna Iyer) * [prim/dv] Enable coverage collection for PRESENT (Udi Jonnalagadda) * [dvsim/syn] Minor fix in message reporting (Michael Schaffner) * [prim] Make prim_clock_inverter a tech specific prim (Michael Schaffner) * [vsg] fix _i/_o for several modules (Scott Johnson) * [doc] Update Licence Headers to fit agreed style (Sam Elliott) * [vsg] fix _i/_o usage on sram_arbiter (Scott Johnson) * [vsg] fix _i/_o usage on prim_fifo (Scott Johnson) * switch to host, primary, or over-arching as appropriate (Scott Johnson) * [dvsim/lint/syn] Properly set the errors_seen value to return nonzero status (Michael Schaffner) * [dvsim] Fix open() call with Pathlib for older Python versions (Michael Schaffner) * [style-lint] Last round of minor fixes to get all targets clean (Michael Schaffner) * [prim] Add shadow register primitive (Pirmin Vogel) * [flash_ctrl] Cosmetic updates enum literals (Srikrishna Iyer) * [tool/script] delete clean section in make files (Cindy Chen) * [dvsim] Add git commit and branch info to reports (Michael Schaffner) * [dvsim/syn/lint] Add options to selectively sanitize reports (Michael Schaffner) * [lint] Update waiver file for prim_generic_pad_wrapper (Michael Schaffner) * [prim_pad_wrapper] Update pad wrapper (Michael Schaffner) * [alert_handler/rtl] priority between ping_ok and sig_int_err (Cindy Chen) * [prim] Add a few prim cells needed for clock / resets (Timothy Chen) * [dv] added default timeout message to DV_SPINWAIT (Srikrishna Iyer) * [dv] Add mechanism to configure vseq via knobs (Srikrishna Iyer) * Make the wmask assertion in prim_generic_ram_*p only apply to writes (Rupert Swarbrick) * [prim_gate_gen] Recalibrate gate generator for new std cells (Michael Schaffner) * [primgen] Use SafeDumper for YAML (Philipp Wagner) * [primgen] Fix some flake8-reported style issues (Philipp Wagner) * [prim] Improve extraction of parameter port list (Philipp Wagner) * [prim] Remove outdated comment from primgen (Philipp Wagner) * Added missing include prim_assert.sv (Dawid Zimonczyk) Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org> |
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Rupert Swarbrick
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1dda6401c3 |
Define an Ibex-specific top_pkg core
The idea is that this can supply top_pkg.sv, a top-level thing in OpenTitan, for DV code we vendor from there. It's probably better to do this than to directly vendor in OpenTitan's top_pkg, because the latter has information about e.g. flash memory layout, which doesn't really have any meaning for Ibex. |
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Philipp Wagner
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ee0a1cf2ce |
Update lowrisc_ip to lowRISC/opentitan@ebf4663b
Update code from upstream repository https://github.com/lowRISC/opentitan to revision ebf4663b42a9d81d026db5821b5c8249d54f23a7 * [prim_lfsr] Fix description in core file for FPV (Philipp Wagner) * [prim_lfsr] Factor out into a separate core file (Philipp Wagner) Signed-off-by: Philipp Wagner <phw@lowrisc.org> |
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Rupert Swarbrick
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45d3790d40 |
Update lowrisc_ip to lowRISC/opentitan@9ac4f9c8
Update code from upstream repository https://github.com/lowRISC/opentitan to revision 9ac4f9c8b924b79eb7d3581b29346a612f705751 * Allow verilated top-levels to do work after a simulation completes (Rupert Swarbrick) * Add some missing dependencies on lowrisc:prim:assert (Rupert Swarbrick) Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org> |
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Philipp Wagner
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711505a17b |
Update lowrisc_ip to lowRISC/opentitan@976d9b9c
Update code from upstream repository https://github.com/lowRISC/opentitan to revision 976d9b9c1f563173d9e4571c775b38e70cb1c5d4 * [lint] Add blanket waiver for DECLFILENAME with blackboxes (Philipp Wagner) * [prim_ram_1p_scr] Add a memory scrambling draft implementation (Michael Schaffner) * [prim_subst_perm] Add simple substitution/permutation network (Michael Schaffner) * [dvsim] Fix for lowRISC/opentitan#2686 - missing else (Srikrishna Iyer) Signed-off-by: Philipp Wagner <phw@lowrisc.org> |
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Rupert Swarbrick
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f35a407906 |
Update lowrisc_ip to lowRISC/opentitan@5cae0cf1
Update code from upstream repository https://github.com/lowRISC/opentitan to revision 5cae0cf1fac783e0d0df8c8597bf65322a696a56 * Allow different assertion "backends" in prim_assert.sv (Rupert Swarbrick) * [prim_prince/doc] Update documentation (Michael Schaffner) * [prim_prince] Add option to instantiate a registers half-way (Michael Schaffner) * [prim_cipher_pkg] Reuse sbox4_8bit to build wider sbox layers (Michael Schaffner) * [dv/prim] add PRESENT testbench (Udi Jonnalagadda) * [uvmdvgen] Scoreboard update. (Srikrishna Iyer) * [flash_ctrl dv] Fix V1 tests (Srikrishna Iyer) * [prim_cipher_pkg] Replicate common subfunctions for other widths (Michael Schaffner) * [prim/present] fix PRESENT decryption bugs (Udi Jonnalagadda) * [prim/present] fix some PRESENT encryption bugs (Udi Jonnalagadda) * [dv] Add get_mem DPI function to Verilator simutil (Stefan Wallentowitz) * [lint/entropy_src] Add the entropy source to the lint regression (Michael Schaffner) * [style-lint] Fix some common style lint warnings (Michael Schaffner) * first set of security checks added to D2 checklist (Scott Johnson) * [fpv/tooling] add FPV class extension in dvsim (Cindy Chen) * [dvsim/lint] Minor fixes for printout issues and result parser status (Michael Schaffner) * [syn] Print detailed messages to .md if publication is disabled (Michael Schaffner) * [prim_util] Do not use $clog2() in Xcelium (Philipp Wagner) * [prim] Update ResetValue parameter in prim_flop_2sync (Timothy Chen) * Modified some command-line arguments for DSim (Aimee Sutton) * [prim_util] Make prim_util a package (Philipp Wagner) * [dv] Move mem checking to scb (Weicai Yang) * [lint] Make PINCONNECTEMPTY Verilator waiver common (Philipp Wagner) * [prim] - Fix generic flash enum reference (Timothy Chen) * [prim_ram_*adv] Mark cfg port as unused (Philipp Wagner) * [prim_fifo_sync] Use vbits() for simpler code (Philipp Wagner) * [prim_flash] Add reset to held_part (Eunchan Kim) * [lint] Add more lint waivers (Philipp Wagner) * [dv] Add random backdoor for csr_hw_reset (Weicai Yang) * [dv] Add set_freq_khz in clk_rst_if (Weicai Yang) * [prim] Close GAPI file handle in primgen (Philipp Wagner) * [fpv/prim_packer] fix CI failure due to index out of bound (Cindy Chen) * [prim_arbiter_*] Propagate parameter changes (Michael Schaffner) * [prim_arbiter_tree] Fix incorrect arbitration behavior (Michael Schaffner) * [prim_arbiter_ppc] Add more FPV fairness checks (Michael Schaffner) * [prim_ram*] Add an assertion that checks wmask consistency (Michael Schaffner) * [memutil] Increase max memory width to 256bit (Tom Roberts) * [flash] - Add flash info page support (Timothy Chen) Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org> |
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Rupert Swarbrick
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8c11bd780c |
Update lowrisc_ip to lowRISC/opentitan@c91b50f3
This is manually squashed with a change to import dv_base_reg too, a new module that was created by Weicai's "csr backdoor support" patch. It's needed because it is a dependency of dv_lib. Update code from upstream repository https://github.com/lowRISC/opentitan to revision c91b50f357a76dae2ada104e397f6a91f72a33da * [prim_ram*_adv] Update core files and add prim_util dependency (Michael Schaffner) * [prim_ram*_adv] Implement Byte parity in prim_ram*_adv (Michael Schaffner) * [dvsim] Run tests in "interleaved" order (Rupert Swarbrick) * [dvsim] Remove unnecessary getattr/setattr calls from SimCfg.py (Rupert Swarbrick) * [dv] Add support for multiple ral models (Srikrishna Iyer) * [rtl] Fix prim flash dependency (Srikrishna Iyer) * [prim_fifo_sync] Make FIFO output zero when empty (Noah Moroze) * [dv] csr backdoor support (Weicai Yang) * [prim] Add a "clog2 width" function (Philipp Wagner) * [dvsim] Allow max-parallel to be set in the environment (Rupert Swarbrick) * [dvsim] Fix --reseed argument (Rupert Swarbrick) * [prim_ram/rom*_adv] Break out into individual core files (Michael Schaffner) * [prim_rom] Align port naming with prim_ram* (Michael Schaffner) * [dv] Allow a test to have "simple" timestamps (Rupert Swarbrick) * [dvsim] Improve --help message (Rupert Swarbrick) * [dvsim] Remove unused --local argument (Rupert Swarbrick) * [dvsim] Small tidy-ups to mode selection in SimCfg.py (Rupert Swarbrick) * [fpv] formal compile fix required by VC Formal (Cindy Chen) * [dvsim] Fix error detection logic in Deploy.py (Rupert Swarbrick) Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org> |
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Rupert Swarbrick
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640a868293 |
Update lowrisc_ip to lowRISC/opentitan@d78da129
Update code from upstream repository https://github.com/lowRISC/opentitan to revision d78da129c7f2b115ccabd1c3af199e0e5812f365 * [dv] Fix loop when waiting for end of run phase in dv_base_monitor (Rupert Swarbrick) * [util] Remove docgen references (Tobias Wölfel) * [dvsim] Small tidy-ups in dvsim.py command line parsing (Rupert Swarbrick) * [dvsim] Tidy up wave dumping logic (Rupert Swarbrick) * [dv/xbar] Add chip-level xbar support (Weicai Yang) * [prim] Fix lint errors (Pirmin Vogel) * [prim] Rework how primgen.py writes out parameter lists for instantiations (Pirmin Vogel) Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org> |
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Philipp Wagner
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b95ff21c28 |
Update lowrisc_ip to lowRISC/opentitan@3f35d4e4
Update code from upstream repository https://github.com/lowRISC/opentitan to revision 3f35d4e42757aeed3f9699d7965f20af41d9d36f * [dv] Initial flash_ctrl DV testbench (Srikrishna Iyer) * [dv] Cleanup Xcelium warning: unconnected port (Srikrishna Iyer) * [dv] Cleanup Xcelium warning: default arg (Srikrishna Iyer) * [dv] Clean up for phase_read_to_end (Weicai Yang) * [DV] Remove urandom from task port (Dawid Zimonczyk) * [doc] Update lint commands in readme (Michael Schaffner) * [dv] Refactor watchdog_ok_to_end (Srikrishna Iyer) Signed-off-by: Philipp Wagner <phw@lowrisc.org> |
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Philipp Wagner
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8b42024cd5 |
Use vendored-in primitives from OpenTitan
Instead of using copies of primitives from OpenTitan, vendor the files in directly from OpenTitan, and use them. Benefits: - Less potential for diverging code between OpenTitan and Ibex, causing problems when importing Ibex into OT. - Use of the abstract primitives instead of the generic ones. The abstract primitives are replaced during synthesis time with target-dependent implementations. For simulation, nothing changes. For synthesis for a given target technology (e.g. a specific ASIC or FPGA technology), the primitives system can be instructed to choose optimized versions (if available). This is most relevant for the icache, which hard-coded the generic SRAM primitive before. This primitive is always implemented as registers. By using the abstract primitive (prim_ram_1p) instead, the RAMs can be replaced with memory-compiler-generated ones if necessary. There are no real draw-backs, but a couple points to be aware of: - Our ram_1p and ram_2p implementations are kept as wrapper around the primitives, since their interface deviates slightly from the one in prim_ram*. This also includes a rather unfortunate naming confusion around rvalid, which means "read data valid" in the OpenTitan advanced RAM primitives (prim_ram_1p_adv for example), but means "ack" in PULP-derived IP and in our bus implementation. - The core_ibex UVM DV doesn't use FuseSoC to generate its file list, but uses a hard-coded list in `ibex_files.f` instead. Since the dynamic primitives system requires the use of FuseSoC we need to provide a stop-gap until this file is removed. Issue #893 tracks progress on that. - Dynamic primitives depend no a not-yet-merged feature of FuseSoC (https://github.com/olofk/fusesoc/pull/391). We depend on the same functionality in OpenTitan and have instructed users to use a patched branch of FuseSoC for a long time through `python-requirements.txt`, so no action is needed for users which are either successfully interacting with the OpenTitan source code, or have followed our instructions. All other users will see a reasonably descriptive error message during a FuseSoC run. - This commit is massive, but there are no good ways to split it into bisectable, yet small, chunks. I'm sorry. Reviewers can safely ignore all code in `vendor/lowrisc_ip`, it's an import from OpenTitan. - The check_tool_requirements tooling isn't easily vendor-able from OpenTitan at the moment. I've filed https://github.com/lowRISC/opentitan/issues/2309 to get that sorted. - The LFSR primitive doesn't have a own core file, forcing us to include the catch-all `lowrisc:prim:all` core. I've filed https://github.com/lowRISC/opentitan/issues/2310 to get that sorted. |
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Philipp Wagner
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3f4e706062 |
Move Verilator simutil upstream to OpenTitan
https://github.com/lowRISC/opentitan/pull/2311 added the Verilator memutils to OpenTitan as upstream. This commit is the second part of the story, removing the code from the Ibex repository, and vendoring it back in from OpenTitan. This also superseded #844, which has now been included through OpenTitan. |
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Rupert Swarbrick
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1bbcce07ca |
Update opentitan vendor imports to lowRISC/opentitan@249b4c31
This commit was generated by running
for hj in $(grep -l opentitan vendor/*.vendor.hjson); do
$opentitan/util/vendor.py -U -c $hj
done
and then squashing together all the resulting commits. It will be
followed by a patch that combines these vendor.hjson files (using the
vendor tool's new "mapping" functionality), but we need a patch first
to get everything in sync before squashing together.
Individual commit messages below:
*****
Update common_ifs to lowRISC/opentitan@249b4c31
Update code from subdir hw/dv/sv/common_ifs in upstream repository
https://github.com/lowRISC/opentitan to revision
249b4c316cd6626d13e17edd8a52ca60c004af96
* [dv] This fixes a padctrl reset issue in the chip level tb (Michael
Schaffner)
*****
Update csr_utils to lowRISC/opentitan@249b4c31
Update code from subdir hw/dv/sv/csr_utils in upstream repository
https://github.com/lowRISC/opentitan to revision
249b4c316cd6626d13e17edd8a52ca60c004af96
* [dv] csr_excl_item printed msg cleanup (Srikrishna Iyer)
* [dv] Fix top-level mem test (Weicai Yang)
* [doc] Fix typo in CSR exclusions (Michael Schaffner)
* [dv] Fix failures in test csr_mem_rw_with_rand_reset (Weicai Yang)
*****
Update dv_lib to lowRISC/opentitan@249b4c31
Update code from subdir hw/dv/sv/dv_lib in upstream repository
https://github.com/lowRISC/opentitan to revision
249b4c316cd6626d13e17edd8a52ca60c004af96
* [dv/chip] fix csr_hw_reset X assertion issue (Cindy Chen)
* [dv] Use phase_ready_to_end to handle end of test (Weicai Yang)
* [dv] Fix failures in test csr_mem_rw_with_rand_reset (Weicai Yang)
*****
Update dv_utils to lowRISC/opentitan@249b4c31
Update code from subdir hw/dv/sv/dv_utils in upstream repository
https://github.com/lowRISC/opentitan to revision
249b4c316cd6626d13e17edd8a52ca60c004af96
* [dv] Use uvm_config_db to control tlul_assert (Weicai Yang)
* [dv] Add begin...end around if statement in macro (Weicai Yang)
* [dv] Fix timeout due to too many non-blocking TL accesses (Weicai
Yang)
* [spi_device/dv] Add interrupt seq (Weicai Yang)
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Update dvsim to lowRISC/opentitan@249b4c31
Update code from subdir util/dvsim in upstream repository
https://github.com/lowRISC/opentitan to revision
249b4c316cd6626d13e17edd8a52ca60c004af96
* [dvsim] Enable round-trip of env variables into log (Philipp Wagner)
* [dvsim] Support for running pre-built SW tests (Srikrishna Iyer)
* [dvsim] Print what cmd is executed in the log (Srikrishna Iyer)
* [dvsim] Specify encoding of opened files as UTF-8 (Philipp Wagner)
* [dvsim] Simplify factory methods for FlowCfg (Rupert Swarbrick)
* [dvsim] small fix on css style (Cindy Chen)
* [dvsim] support css format for email (Cindy Chen)
* [doc] Rename Hardware -> Development Stages (Sam Elliott)
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Update uvmdvgen to lowRISC/opentitan@249b4c31
Update code from subdir util/uvmdvgen in upstream repository
https://github.com/lowRISC/opentitan to revision
249b4c316cd6626d13e17edd8a52ca60c004af96
* [uvmdvgen] Minor env gen fix (Srikrishna Iyer)
* [doc] Rename Hardware -> Development Stages (Sam Elliott)
* [dv] Use uvm_config_db to control tlul_assert (Weicai Yang)
* [uvmdvgen] Automate checklist gen, fixes (Srikrishna Iyer)
* [doc] Unify dashboard, manual spec table (Srikrishna Iyer)
* [dvsim] Added fusesoc generator for RAL (Srikrishna Iyer)
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Rupert Swarbrick
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6a557b47ee |
Update dvsim to lowRISC/opentitan@1d17b122
Update code from subdir util/dvsim in upstream repository https://github.com/lowRISC/opentitan to revision 1d17b1225d324c81da522c69317335a83edd5ddb * [dvsim] PEP8 fixes in dvsim (Rupert Swarbrick) * [dvsim] Fix PEP8 error and slightly tidy code in testplan_utils.py (Rupert Swarbrick) * [dvsim] Correct bug in regression creation in dvsim's Modes.py (Rupert Swarbrick) * [dv] Enable xcelium coverage publish (Weicai Yang) * [tool/dvsim] Enable Xcelium coverage and clean up email arg (Cindy Chen) * [dv] add send email option to dvsim.py (Cindy Chen) * [util/dvsim] Convert time to UTC timezone (Eunchan Kim) * [dvsim] Fix broken link of xbar testplan (Weicai Yang) * [dvsim] Add CTRL-C support (Weicai Yang) * [dvsim] Initial verible lint integration (Michael Schaffner) * [dvsim] Add control of max job submission per second (Weicai Yang) * [dv/tool] Add support to choose sub-cfgs (Cindy Chen) * [dvsim] Enable coverage collection with Xcelium (Srikrishna Iyer) * [dvsim] Update lint flow due to changes in synthesis (Michael Schaffner) * [dvsim] Synthesis target integration (Michael Schaffner) * [dvsim] Added fusesoc generator for RAL (Srikrishna Iyer) * [dvsim] Fix summary table (Greg Chadwick) Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org> |
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Rupert Swarbrick
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39b6bdf2a3 |
Update dv_lib to lowRISC/opentitan@1d17b122
Update code from subdir hw/dv/sv/dv_lib in upstream repository https://github.com/lowRISC/opentitan to revision 1d17b1225d324c81da522c69317335a83edd5ddb * [dv] Add excl for rstmgr, pwrmgr and fix top-level csr test (Weicai Yang) * [dv] Allow dv_lib-based sequences to have different RSP/REQ types (Rupert Swarbrick) * [dv] Support WO, RO type for mem (Weicai Yang) * [dv,sw] SW -> DV tb self-checking mechanism - SV (Srikrishna Iyer) * [dv/top] Fix csr rw test (Cindy Chen) Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org> |
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udinator
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f69c6fbabd
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[dv] initial icache testbench (#711)
* [dv] add vendor .hjson files for dv tools Signed-off-by: Udi Jonnalagadda <udij@google.com> * Update common_ifs to lowRISC/opentitan@0d7f7ac7 Update code from subdir hw/dv/sv/common_ifs in upstream repository https://github.com/lowRISC/opentitan to revision 0d7f7ac755d4e00811257027dd814edb2afca050 Signed-off-by: Udi Jonnalagadda <udij@google.com> * Update csr_utils to lowRISC/opentitan@0d7f7ac7 Update code from subdir hw/dv/sv/csr_utils in upstream repository https://github.com/lowRISC/opentitan to revision 0d7f7ac755d4e00811257027dd814edb2afca050 Signed-off-by: Udi Jonnalagadda <udij@google.com> * Update dv_lib to lowRISC/opentitan@0d7f7ac7 Update code from subdir hw/dv/sv/dv_lib in upstream repository https://github.com/lowRISC/opentitan to revision 0d7f7ac755d4e00811257027dd814edb2afca050 Signed-off-by: Udi Jonnalagadda <udij@google.com> * Update dvsim to lowRISC/opentitan@0d7f7ac7 Update code from subdir util/dvsim in upstream repository https://github.com/lowRISC/opentitan to revision 0d7f7ac755d4e00811257027dd814edb2afca050 Signed-off-by: Udi Jonnalagadda <udij@google.com> * Update uvmdvgen to lowRISC/opentitan@0d7f7ac7 Update code from subdir util/uvmdvgen in upstream repository https://github.com/lowRISC/opentitan to revision 0d7f7ac755d4e00811257027dd814edb2afca050 Signed-off-by: Udi Jonnalagadda <udij@google.com> * Update dv_utils to lowRISC/opentitan@0d7f7ac7 Update code from subdir hw/dv/sv/dv_utils in upstream repository https://github.com/lowRISC/opentitan to revision 0d7f7ac755d4e00811257027dd814edb2afca050 Signed-off-by: Udi Jonnalagadda <udij@google.com> * [dv] initial icache testbench Signed-off-by: Udi Jonnalagadda <udij@google.com> * [dv] add top_pkg and its core file to icache/dv Signed-off-by: Udi Jonnalagadda <udij@google.com> * [dv] update ibex_core and ibex_icache corefile dependencies Signed-off-by: Udi Jonnalagadda <udij@google.com> * [dv] add .vpd support for wave-dumping Signed-off-by: Udi Jonnalagadda <udij@google.com> |